board/technexion/pico-imx6ul/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <common.h>
   4 #include <cpu_func.h>
   5 #include <init.h>
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/iomux.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/crm_regs.h>
  10 #include <asm/arch/mx6ul_pins.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/boot_mode.h>
  16 #include <fsl_esdhc_imx.h>
  17 #include <linux/libfdt.h>
  18 #include <spl.h>
  19
  20 #if defined(CONFIG_SPL_BUILD)
  21
  22 #ifdef CONFIG_SPL_OS_BOOT
  23 int spl_start_uboot(void)
  24 {
  25         /* Break into full U-Boot on 'c' */
  26         if (serial_tstc() && serial_getc() == 'c')
  27                 return 1;
  28
  29         return 0;
  30 }
  31 #endif
  32
  33 #include <asm/arch/mx6-ddr.h>
  34
  35 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  36         .grp_addds = 0x00000030,
  37         .grp_ddrmode_ctl = 0x00020000,
  38         .grp_b0ds = 0x00000030,
  39         .grp_ctlds = 0x00000030,
  40         .grp_b1ds = 0x00000030,
  41         .grp_ddrpke = 0x00000000,
  42         .grp_ddrmode = 0x00020000,
  43         .grp_ddr_type = 0x00080000,
  44 };
  45
  46 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  47         .dram_dqm0 = 0x00000030,
  48         .dram_dqm1 = 0x00000030,
  49         .dram_ras = 0x00000030,
  50         .dram_cas = 0x00000030,
  51         .dram_odt0 = 0x00000030,
  52         .dram_odt1 = 0x00000030,
  53         .dram_sdba2 = 0x00000000,
  54         .dram_sdclk_0 = 0x00000030,
  55         .dram_sdqs0 = 0x00000030,
  56         .dram_sdqs1 = 0x00000030,
  57         .dram_reset = 0x00000030,
  58 };
  59
  60 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  61         .p0_mpwldectrl0 = 0x00000000,
  62         .p0_mpdgctrl0 = 0x01380134,
  63         .p0_mprddlctl = 0x40404244,
  64         .p0_mpwrdlctl = 0x40405050,
  65 };
  66
  67 static struct mx6_ddr_sysinfo ddr_sysinfo = {
  68         .dsize          = 0,
  69         .cs1_mirror     = 0,
  70         .cs_density     = 32,
  71         .ncs            = 1,
  72         .bi_on          = 1,
  73         .rtt_nom        = 1,
  74         .rtt_wr         = 0,
  75         .ralat          = 5,
  76         .walat          = 0,
  77         .mif3_mode      = 3,
  78         .rst_to_cke     = 0x23,
  79         .sde_to_rst     = 0x10,
  80         .refsel = 1,
  81         .refr = 3,
  82 };
  83
  84 static struct mx6_ddr3_cfg mem_ddr = {
  85         .mem_speed = 1333,
  86         .density = 2,
  87         .width = 16,
  88         .banks = 8,
  89         .coladdr = 10,
  90         .pagesz = 2,
  91         .trcd = 1350,
  92         .trcmin = 4950,
  93         .trasmin = 3600,
  94 };
  95
  96 static void ccgr_init(void)
  97 {
  98         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  99
 100         writel(0xFFFFFFFF, &ccm->CCGR0);
 101         writel(0xFFFFFFFF, &ccm->CCGR1);
 102         writel(0xFFFFFFFF, &ccm->CCGR2);
 103         writel(0xFFFFFFFF, &ccm->CCGR3);
 104         writel(0xFFFFFFFF, &ccm->CCGR4);
 105         writel(0xFFFFFFFF, &ccm->CCGR5);
 106         writel(0xFFFFFFFF, &ccm->CCGR6);
 107 }
 108
 109 static void imx6ul_spl_dram_cfg_size(u32 ram_size)
 110 {
 111         if (ram_size == SZ_256M)
 112                 mem_ddr.rowaddr = 14;
 113         else
 114                 mem_ddr.rowaddr = 15;
 115
 116         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 117         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 118 }
 119
 120 static void imx6ul_spl_dram_cfg(void)
 121 {
 122         ulong ram_size_test, ram_size = 0;
 123
 124         for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
 125                 imx6ul_spl_dram_cfg_size(ram_size);
 126                 ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
 127                 if (ram_size_test == ram_size)
 128                         break;
 129         }
 130
 131         if (ram_size < SZ_256M) {
 132                 puts("ERROR: DRAM size detection failed\n");
 133                 hang();
 134         }
 135 }
 136
 137 void board_init_f(ulong dummy)
 138 {
 139         ccgr_init();
 140         arch_cpu_init();
 141         board_early_init_f();
 142         timer_init();
 143         preloader_console_init();
 144         imx6ul_spl_dram_cfg();
 145         memset(__bss_start, 0, __bss_end - __bss_start);
 146         board_init_r(NULL, 0);
 147 }
 148
 149 void reset_cpu(ulong addr)
 150 {
 151 }
 152
 153 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 154         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 155         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 156
 157 static iomux_v3_cfg_t const usdhc1_pads[] = {
 158         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 159         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 160         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168 };
 169
 170 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 171         {USDHC1_BASE_ADDR},
 172 };
 173
 174 int board_mmc_getcd(struct mmc *mmc)
 175 {
 176         return 1;
 177 }
 178
 179 int board_mmc_init(bd_t *bis)
 180 {
 181         imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 182         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 183         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 184 }
 185 #endif