1 // SPDX-License-Identifier: GPL-2.0+
4 #include <asm/arch/clock.h>
5 #include <asm/arch/iomux.h>
6 #include <asm/arch/imx-regs.h>
7 #include <asm/arch/crm_regs.h>
8 #include <asm/arch/mx6ul_pins.h>
9 #include <asm/arch/mx6-pins.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/mach-imx/boot_mode.h>
14 #include <fsl_esdhc_imx.h>
15 #include <linux/libfdt.h>
18 #if defined(CONFIG_SPL_BUILD)
20 #ifdef CONFIG_SPL_OS_BOOT
21 int spl_start_uboot(void)
23 /* Break into full U-Boot on 'c' */
24 if (serial_tstc() && serial_getc() == 'c')
31 #include <asm/arch/mx6-ddr.h>
33 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
34 .grp_addds = 0x00000030,
35 .grp_ddrmode_ctl = 0x00020000,
36 .grp_b0ds = 0x00000030,
37 .grp_ctlds = 0x00000030,
38 .grp_b1ds = 0x00000030,
39 .grp_ddrpke = 0x00000000,
40 .grp_ddrmode = 0x00020000,
41 .grp_ddr_type = 0x00080000,
44 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
45 .dram_dqm0 = 0x00000030,
46 .dram_dqm1 = 0x00000030,
47 .dram_ras = 0x00000030,
48 .dram_cas = 0x00000030,
49 .dram_odt0 = 0x00000030,
50 .dram_odt1 = 0x00000030,
51 .dram_sdba2 = 0x00000000,
52 .dram_sdclk_0 = 0x00000030,
53 .dram_sdqs0 = 0x00000030,
54 .dram_sdqs1 = 0x00000030,
55 .dram_reset = 0x00000030,
58 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
59 .p0_mpwldectrl0 = 0x00000000,
60 .p0_mpdgctrl0 = 0x01380134,
61 .p0_mprddlctl = 0x40404244,
62 .p0_mpwrdlctl = 0x40405050,
65 static struct mx6_ddr_sysinfo ddr_sysinfo = {
82 static struct mx6_ddr3_cfg mem_ddr = {
94 static void ccgr_init(void)
96 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
98 writel(0xFFFFFFFF, &ccm->CCGR0);
99 writel(0xFFFFFFFF, &ccm->CCGR1);
100 writel(0xFFFFFFFF, &ccm->CCGR2);
101 writel(0xFFFFFFFF, &ccm->CCGR3);
102 writel(0xFFFFFFFF, &ccm->CCGR4);
103 writel(0xFFFFFFFF, &ccm->CCGR5);
104 writel(0xFFFFFFFF, &ccm->CCGR6);
107 static void imx6ul_spl_dram_cfg_size(u32 ram_size)
109 if (ram_size == SZ_256M)
110 mem_ddr.rowaddr = 14;
112 mem_ddr.rowaddr = 15;
114 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
115 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
118 static void imx6ul_spl_dram_cfg(void)
120 ulong ram_size_test, ram_size = 0;
122 for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
123 imx6ul_spl_dram_cfg_size(ram_size);
124 ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
125 if (ram_size_test == ram_size)
129 if (ram_size < SZ_256M) {
130 puts("ERROR: DRAM size detection failed\n");
135 void board_init_f(ulong dummy)
139 board_early_init_f();
141 preloader_console_init();
142 imx6ul_spl_dram_cfg();
143 memset(__bss_start, 0, __bss_end - __bss_start);
144 board_init_r(NULL, 0);
147 void reset_cpu(ulong addr)
151 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
152 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
153 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
155 static iomux_v3_cfg_t const usdhc1_pads[] = {
156 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
168 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
172 int board_mmc_getcd(struct mmc *mmc)
177 int board_mmc_init(bd_t *bis)
179 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
180 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
181 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);