board/technexion/pico-imx6ul/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <common.h>
   4 #include <cpu_func.h>
   5 #include <hang.h>
   6 #include <init.h>
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/iomux.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/mx6ul_pins.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <fsl_esdhc_imx.h>
  18 #include <linux/libfdt.h>
  19 #include <spl.h>
  20
  21 #if defined(CONFIG_SPL_BUILD)
  22
  23 #ifdef CONFIG_SPL_OS_BOOT
  24 int spl_start_uboot(void)
  25 {
  26         /* Break into full U-Boot on 'c' */
  27         if (serial_tstc() && serial_getc() == 'c')
  28                 return 1;
  29
  30         return 0;
  31 }
  32 #endif
  33
  34 #include <asm/arch/mx6-ddr.h>
  35
  36 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  37         .grp_addds = 0x00000030,
  38         .grp_ddrmode_ctl = 0x00020000,
  39         .grp_b0ds = 0x00000030,
  40         .grp_ctlds = 0x00000030,
  41         .grp_b1ds = 0x00000030,
  42         .grp_ddrpke = 0x00000000,
  43         .grp_ddrmode = 0x00020000,
  44         .grp_ddr_type = 0x00080000,
  45 };
  46
  47 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  48         .dram_dqm0 = 0x00000030,
  49         .dram_dqm1 = 0x00000030,
  50         .dram_ras = 0x00000030,
  51         .dram_cas = 0x00000030,
  52         .dram_odt0 = 0x00000030,
  53         .dram_odt1 = 0x00000030,
  54         .dram_sdba2 = 0x00000000,
  55         .dram_sdclk_0 = 0x00000030,
  56         .dram_sdqs0 = 0x00000030,
  57         .dram_sdqs1 = 0x00000030,
  58         .dram_reset = 0x00000030,
  59 };
  60
  61 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  62         .p0_mpwldectrl0 = 0x00000000,
  63         .p0_mpdgctrl0 = 0x01380134,
  64         .p0_mprddlctl = 0x40404244,
  65         .p0_mpwrdlctl = 0x40405050,
  66 };
  67
  68 static struct mx6_ddr_sysinfo ddr_sysinfo = {
  69         .dsize          = 0,
  70         .cs1_mirror     = 0,
  71         .cs_density     = 32,
  72         .ncs            = 1,
  73         .bi_on          = 1,
  74         .rtt_nom        = 1,
  75         .rtt_wr         = 0,
  76         .ralat          = 5,
  77         .walat          = 0,
  78         .mif3_mode      = 3,
  79         .rst_to_cke     = 0x23,
  80         .sde_to_rst     = 0x10,
  81         .refsel = 1,
  82         .refr = 3,
  83 };
  84
  85 static struct mx6_ddr3_cfg mem_ddr = {
  86         .mem_speed = 1333,
  87         .density = 2,
  88         .width = 16,
  89         .banks = 8,
  90         .coladdr = 10,
  91         .pagesz = 2,
  92         .trcd = 1350,
  93         .trcmin = 4950,
  94         .trasmin = 3600,
  95 };
  96
  97 static void ccgr_init(void)
  98 {
  99         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 100
 101         writel(0xFFFFFFFF, &ccm->CCGR0);
 102         writel(0xFFFFFFFF, &ccm->CCGR1);
 103         writel(0xFFFFFFFF, &ccm->CCGR2);
 104         writel(0xFFFFFFFF, &ccm->CCGR3);
 105         writel(0xFFFFFFFF, &ccm->CCGR4);
 106         writel(0xFFFFFFFF, &ccm->CCGR5);
 107         writel(0xFFFFFFFF, &ccm->CCGR6);
 108 }
 109
 110 static void imx6ul_spl_dram_cfg_size(u32 ram_size)
 111 {
 112         if (ram_size == SZ_256M)
 113                 mem_ddr.rowaddr = 14;
 114         else
 115                 mem_ddr.rowaddr = 15;
 116
 117         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 118         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 119 }
 120
 121 static void imx6ul_spl_dram_cfg(void)
 122 {
 123         ulong ram_size_test, ram_size = 0;
 124
 125         for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
 126                 imx6ul_spl_dram_cfg_size(ram_size);
 127                 ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
 128                 if (ram_size_test == ram_size)
 129                         break;
 130         }
 131
 132         if (ram_size < SZ_256M) {
 133                 puts("ERROR: DRAM size detection failed\n");
 134                 hang();
 135         }
 136 }
 137
 138 void board_init_f(ulong dummy)
 139 {
 140         ccgr_init();
 141         arch_cpu_init();
 142         board_early_init_f();
 143         timer_init();
 144         preloader_console_init();
 145         imx6ul_spl_dram_cfg();
 146         memset(__bss_start, 0, __bss_end - __bss_start);
 147         board_init_r(NULL, 0);
 148 }
 149
 150 void reset_cpu(ulong addr)
 151 {
 152 }
 153
 154 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 155         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 156         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 157
 158 static iomux_v3_cfg_t const usdhc1_pads[] = {
 159         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 160         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169 };
 170
 171 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 172         {USDHC1_BASE_ADDR},
 173 };
 174
 175 int board_mmc_getcd(struct mmc *mmc)
 176 {
 177         return 1;
 178 }
 179
 180 int board_mmc_init(bd_t *bis)
 181 {
 182         imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 183         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 184         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 185 }
 186 #endif