1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Technexion Ltd.
5 * Author: Richard Hu <richard.hu@technexion.com>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/iomux-v3.h>
20 #include <linux/sizes.h>
22 #include <power/pmic.h>
23 #include <power/pfuze3000_pmic.h>
24 #include "../../freescale/common/pfuze.h"
26 DECLARE_GLOBAL_DATA_PTR;
28 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
29 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
30 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
33 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
34 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
37 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
39 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
40 PAD_CTL_SPEED_HIGH | \
41 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
43 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
45 #define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
47 static iomux_v3_cfg_t const fec_pads[] = {
48 MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
49 MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
50 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
51 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
52 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
53 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
54 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
55 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
56 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
57 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
58 MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
61 static void setup_iomux_fec(void)
63 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
66 int board_eth_init(bd_t *bis)
70 gpio_request(RMII_PHY_RESET, "enet_phy_reset");
71 gpio_direction_output(RMII_PHY_RESET, 0);
73 * According to KSZ8081MNX-RNB manual:
74 * For warm reset, the reset (RST#) pin should be asserted low for a
75 * minimum of 500μs. The strap-in pin values are read and updated
76 * at the de-assertion of reset.
80 gpio_direction_output(RMII_PHY_RESET, 1);
82 * According to KSZ8081MNX-RNB manual:
83 * After the de-assertion of reset, wait a minimum of 100μs before
84 * starting programming on the MIIM (MDC/MDIO) interface.
88 return fecmxc_initialize(bis);
91 static int setup_fec(void)
93 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
96 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
97 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
99 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
108 int board_phy_config(struct phy_device *phydev)
110 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
112 if (phydev->drv->config)
113 phydev->drv->config(phydev);
120 gd->ram_size = imx_ddr_size();
125 static iomux_v3_cfg_t const uart6_pads[] = {
126 MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
127 MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
130 #define USB_OTHERREGS_OFFSET 0x800
131 #define UCTRL_PWR_POL (1 << 9)
133 static iomux_v3_cfg_t const usb_otg_pad[] = {
134 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
137 static void setup_iomux_uart(void)
139 imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
142 static void setup_usb(void)
144 imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
147 int board_early_init_f(void)
154 #ifdef CONFIG_DM_PMIC
155 int power_init_board(void)
158 int ret, dev_id, rev_id;
160 ret = pmic_get("pfuze3000", &dev);
166 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
167 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
168 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
170 /* disable Low Power Mode during standby mode */
171 pmic_reg_write(dev, PFUZE3000_LDOGCTL, 0x1);
173 /* SW1B step ramp up time from 2us to 4us/25mV */
174 pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
176 /* SW1B mode to APS/PFM */
177 pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
179 /* SW1B standby voltage set to 0.975V */
180 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
186 int board_usb_phy_mode(int port)
189 return USB_INIT_HOST;
191 return USB_INIT_DEVICE;
194 int board_ehci_hcd_init(int port)
201 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
204 /* Set Power polarity */
205 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
212 /* Address of boot parameters */
213 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
223 puts("Board: PICO-IMX6UL-EMMC\n");