1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Technexion Ltd.
5 * Author: Richard Hu <richard.hu@technexion.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/iomux-v3.h>
21 #include <linux/sizes.h>
23 #include <power/pmic.h>
24 #include <power/pfuze3000_pmic.h>
25 #include "../../freescale/common/pfuze.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
30 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
31 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
34 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
35 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
38 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
41 PAD_CTL_SPEED_HIGH | \
42 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
44 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
46 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
47 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
49 #define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
51 static iomux_v3_cfg_t const fec_pads[] = {
52 MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
53 MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
54 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
55 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
56 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
57 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
58 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
59 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
62 MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
65 static void setup_iomux_fec(void)
67 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
70 int board_eth_init(bd_t *bis)
74 gpio_request(RMII_PHY_RESET, "enet_phy_reset");
75 gpio_direction_output(RMII_PHY_RESET, 0);
77 * According to KSZ8081MNX-RNB manual:
78 * For warm reset, the reset (RST#) pin should be asserted low for a
79 * minimum of 500μs. The strap-in pin values are read and updated
80 * at the de-assertion of reset.
84 gpio_direction_output(RMII_PHY_RESET, 1);
86 * According to KSZ8081MNX-RNB manual:
87 * After the de-assertion of reset, wait a minimum of 100μs before
88 * starting programming on the MIIM (MDC/MDIO) interface.
92 return fecmxc_initialize(bis);
95 static int setup_fec(void)
97 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
100 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
101 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
103 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
112 #ifdef CONFIG_VIDEO_MXS
113 static iomux_v3_cfg_t const lcd_pads[] = {
114 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
115 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
116 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
117 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
118 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
119 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
120 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
121 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
122 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
123 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
124 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
125 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
126 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
127 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
128 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
129 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
130 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
131 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
132 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
133 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
134 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
135 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
136 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
137 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
138 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
139 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
140 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
141 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
142 /* LCD_BLT_CTRL: GPIO for Brightness adjustment */
143 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
144 /* LCD_VDD_EN: LCD enabled */
145 MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
150 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
151 gpio_request(IMX_GPIO_NR(4, 10), "lcd_brightness");
152 gpio_request(IMX_GPIO_NR(1, 11), "lcd_enable");
153 /* Set Brightness to high */
154 gpio_direction_output(IMX_GPIO_NR(4, 10) , 1);
155 /* Set LCD enable to high */
156 gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
160 int board_phy_config(struct phy_device *phydev)
162 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
164 if (phydev->drv->config)
165 phydev->drv->config(phydev);
172 gd->ram_size = imx_ddr_size();
177 static iomux_v3_cfg_t const uart6_pads[] = {
178 MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
179 MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
182 #define USB_OTHERREGS_OFFSET 0x800
183 #define UCTRL_PWR_POL (1 << 9)
185 static iomux_v3_cfg_t const usb_otg_pad[] = {
186 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
189 static void setup_iomux_uart(void)
191 imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
194 static void setup_usb(void)
196 imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
199 int board_early_init_f(void)
206 #ifdef CONFIG_DM_PMIC
207 int power_init_board(void)
210 int ret, dev_id, rev_id;
212 ret = pmic_get("pfuze3000", &dev);
218 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
219 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
220 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
222 /* disable Low Power Mode during standby mode */
223 pmic_reg_write(dev, PFUZE3000_LDOGCTL, 0x1);
225 /* SW1B step ramp up time from 2us to 4us/25mV */
226 pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
228 /* SW1B mode to APS/PFM */
229 pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
231 /* SW1B standby voltage set to 0.975V */
232 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
238 int board_usb_phy_mode(int port)
241 return USB_INIT_HOST;
243 return USB_INIT_DEVICE;
246 int board_ehci_hcd_init(int port)
253 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
256 /* Set Power polarity */
257 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
264 /* Address of boot parameters */
265 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
269 #ifdef CONFIG_VIDEO_MXS
277 puts("Board: PICO-IMX6UL-EMMC\n");