1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Technexion Ltd.
5 * Author: Richard Hu <richard.hu@technexion.com>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/mxc_i2c.h>
22 #include <linux/sizes.h>
24 #include <power/pmic.h>
25 #include <power/pfuze3000_pmic.h>
26 #include "../../freescale/common/pfuze.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
39 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
44 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
46 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
47 PAD_CTL_SPEED_HIGH | \
48 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
50 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
52 #define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
54 #ifdef CONFIG_SYS_I2C_MXC
55 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
57 struct i2c_pads_info i2c_pad_info1 = {
59 .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
60 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
61 .gp = IMX_GPIO_NR(1, 2),
64 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
65 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
66 .gp = IMX_GPIO_NR(1, 3),
71 static iomux_v3_cfg_t const fec_pads[] = {
72 MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
73 MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
74 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
77 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
85 static void setup_iomux_fec(void)
87 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
90 int board_eth_init(bd_t *bis)
94 gpio_request(RMII_PHY_RESET, "enet_phy_reset");
95 gpio_direction_output(RMII_PHY_RESET, 0);
97 * According to KSZ8081MNX-RNB manual:
98 * For warm reset, the reset (RST#) pin should be asserted low for a
99 * minimum of 500μs. The strap-in pin values are read and updated
100 * at the de-assertion of reset.
104 gpio_direction_output(RMII_PHY_RESET, 1);
106 * According to KSZ8081MNX-RNB manual:
107 * After the de-assertion of reset, wait a minimum of 100μs before
108 * starting programming on the MIIM (MDC/MDIO) interface.
112 return fecmxc_initialize(bis);
115 static int setup_fec(void)
117 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
120 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
121 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
123 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
132 int board_phy_config(struct phy_device *phydev)
134 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
136 if (phydev->drv->config)
137 phydev->drv->config(phydev);
144 gd->ram_size = imx_ddr_size();
149 static iomux_v3_cfg_t const uart6_pads[] = {
150 MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
151 MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
154 #define USB_OTHERREGS_OFFSET 0x800
155 #define UCTRL_PWR_POL (1 << 9)
157 static iomux_v3_cfg_t const usb_otg_pad[] = {
158 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
161 static void setup_iomux_uart(void)
163 imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
166 static void setup_usb(void)
168 imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
171 int board_early_init_f(void)
180 static struct pmic *pfuze;
181 int power_init_board(void)
184 unsigned int reg, rev_id;
186 ret = power_pfuze3000_init(I2C_PMIC);
190 pfuze = pmic_get("PFUZE3000");
191 ret = pmic_probe(pfuze);
195 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
196 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
197 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
199 /* disable Low Power Mode during standby mode */
200 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
202 /* SW1B step ramp up time from 2us to 4us/25mV */
203 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40);
205 /* SW1B mode to APS/PFM */
206 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc);
208 /* SW1B standby voltage set to 0.975V */
209 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb);
215 int board_usb_phy_mode(int port)
218 return USB_INIT_HOST;
220 return USB_INIT_DEVICE;
223 int board_ehci_hcd_init(int port)
230 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
233 /* Set Power polarity */
234 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
241 /* Address of boot parameters */
242 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
244 #ifdef CONFIG_SYS_I2C_MXC
245 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
256 puts("Board: PICO-IMX6UL-EMMC\n");