board/technexion/pico-imx6/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Technexion Ltd.
   4  *
   5  * Author: Richard Hu <richard.hu@technexion.com>
   6  *         Fabio Estevam <festevam@gmail.com>
   7  */
   8
   9 #include <common.h>
  10 #include <image.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <linux/errno.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc_imx.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <spl.h>
  25
  26 #if defined(CONFIG_SPL_BUILD)
  27 #include <asm/arch/mx6-ddr.h>
  28
  29 #define IMX6DQ_DRIVE_STRENGTH           0x30
  30 #define IMX6SDL_DRIVE_STRENGTH          0x28
  31
  32 #ifdef CONFIG_SPL_OS_BOOT
  33 int spl_start_uboot(void)
  34 {
  35         /* Break into full U-Boot on 'c' */
  36         if (serial_tstc() && serial_getc() == 'c')
  37                 return 1;
  38
  39         return 0;
  40 }
  41 #endif
  42
  43 /* configure MX6Q/DUAL mmdc DDR io registers */
  44 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  45         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  46         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  47         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  48         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  49         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  50         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  51         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  52         .dram_sdba2 = 0x00000000,
  53         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  54         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  55         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  56         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  57         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  58         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  59         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  60         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  61         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  62         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  63         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  64         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  65         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  66         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  67         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  68         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  69         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  70         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  71 };
  72
  73 /* configure MX6Q/DUAL mmdc GRP io registers */
  74 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  75         .grp_ddr_type = 0x000c0000,
  76         .grp_ddrmode_ctl = 0x00020000,
  77         .grp_ddrpke = 0x00000000,
  78         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  79         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  80         .grp_ddrmode = 0x00020000,
  81         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  82         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  83         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  84         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  85         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  86         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  87         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  88         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  89 };
  90
  91 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  92 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  93         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  94         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  95         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  96         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  97         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  98         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  99         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 100         .dram_sdba2 = 0x00000000,
 101         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 102         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 103         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 104         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 105         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 106         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 107         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 108         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 109         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 110         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 111         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 112         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 113         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 114         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 115         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 116         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 117         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 118         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 119 };
 120
 121 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 122 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 123         .grp_ddr_type = 0x000c0000,
 124         .grp_ddrmode_ctl = 0x00020000,
 125         .grp_ddrpke = 0x00000000,
 126         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 127         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 128         .grp_ddrmode = 0x00020000,
 129         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 130         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 131         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 132         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 133         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 134         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 135         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 136         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 137 };
 138
 139 /* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */
 140 static struct mx6_ddr3_cfg h5t04g63afr = {
 141         .mem_speed = 800,
 142         .density = 4,
 143         .width = 16,
 144         .banks = 8,
 145         .rowaddr = 15,
 146         .coladdr = 10,
 147         .pagesz = 2,
 148         .trcd = 1500,
 149         .trcmin = 5250,
 150         .trasmin = 3750,
 151 };
 152
 153 /* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */
 154 static struct mx6_ddr3_cfg h5tq2g63ffr = {
 155         .mem_speed = 800,
 156         .density = 2,
 157         .width = 16,
 158         .banks = 8,
 159         .rowaddr = 14,
 160         .coladdr = 10,
 161         .pagesz = 2,
 162         .trcd = 1500,
 163         .trcmin = 5250,
 164         .trasmin = 3750,
 165 };
 166
 167 static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
 168         .p0_mpwldectrl0 = 0x00000000,
 169         .p0_mpwldectrl1 = 0x00000000,
 170         .p1_mpwldectrl0 = 0x00000000,
 171         .p1_mpwldectrl1 = 0x00000000,
 172         .p0_mpdgctrl0 = 0x032C0340,
 173         .p0_mpdgctrl1 = 0x03300324,
 174         .p1_mpdgctrl0 = 0x032C0338,
 175         .p1_mpdgctrl1 = 0x03300274,
 176         .p0_mprddlctl = 0x423A383E,
 177         .p1_mprddlctl = 0x3638323E,
 178         .p0_mpwrdlctl = 0x363C4640,
 179         .p1_mpwrdlctl = 0x4034423C,
 180 };
 181
 182 /* DDR 32bit */
 183 static struct mx6_ddr_sysinfo mem_s = {
 184         .dsize          = 1,
 185         .cs1_mirror     = 0,
 186         /* config for full 4GB range so that get_mem_size() works */
 187         .cs_density     = 32,
 188         .ncs            = 1,
 189         .bi_on          = 1,
 190         .rtt_nom        = 1,
 191         .rtt_wr         = 0,
 192         .ralat          = 5,
 193         .walat          = 0,
 194         .mif3_mode      = 3,
 195         .rst_to_cke     = 0x23,
 196         .sde_to_rst     = 0x10,
 197 };
 198
 199 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 200         .p0_mpwldectrl0 = 0x001f001f,
 201         .p0_mpwldectrl1 = 0x001f001f,
 202         .p1_mpwldectrl0 = 0x001f001f,
 203         .p1_mpwldectrl1 = 0x001f001f,
 204         .p0_mpdgctrl0 = 0x420e020e,
 205         .p0_mpdgctrl1 = 0x02000200,
 206         .p1_mpdgctrl0 = 0x42020202,
 207         .p1_mpdgctrl1 = 0x01720172,
 208         .p0_mprddlctl = 0x494c4f4c,
 209         .p1_mprddlctl = 0x4a4c4c49,
 210         .p0_mpwrdlctl = 0x3f3f3133,
 211         .p1_mpwrdlctl = 0x39373f2e,
 212 };
 213
 214 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
 215         .p0_mpwldectrl0 = 0x0040003c,
 216         .p0_mpwldectrl1 = 0x0032003e,
 217         .p0_mpdgctrl0 = 0x42350231,
 218         .p0_mpdgctrl1 = 0x021a0218,
 219         .p0_mprddlctl = 0x4b4b4e49,
 220         .p0_mpwrdlctl = 0x3f3f3035,
 221 };
 222
 223 static void ccgr_init(void)
 224 {
 225         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 226
 227         writel(0x00C03F3F, &ccm->CCGR0);
 228         writel(0x0030FC03, &ccm->CCGR1);
 229         writel(0x0FFFC000, &ccm->CCGR2);
 230         writel(0x3FF03000, &ccm->CCGR3);
 231         writel(0x00FFF300, &ccm->CCGR4);
 232         writel(0x0F0000C3, &ccm->CCGR5);
 233         writel(0x000003FF, &ccm->CCGR6);
 234 }
 235
 236 static void spl_dram_init(void)
 237 {
 238         if (is_mx6solo()) {
 239                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 240                 mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr);
 241         } else if (is_mx6dl()) {
 242                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 243                 mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr);
 244         } else if (is_mx6dq()) {
 245                 mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 246                 mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr);
 247         }
 248
 249         udelay(100);
 250 }
 251
 252 void board_init_f(ulong dummy)
 253 {
 254         ccgr_init();
 255
 256         /* setup AIPS and disable watchdog */
 257         arch_cpu_init();
 258
 259         gpr_init();
 260
 261         /* iomux */
 262         board_early_init_f();
 263
 264         /* setup GP timer */
 265         timer_init();
 266
 267         /* UART clocks enabled and gd valid - init serial console */
 268         preloader_console_init();
 269
 270         /* DDR initialization */
 271         spl_dram_init();
 272 }
 273
 274 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
 275         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
 276         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 277
 278 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 279         {USDHC3_BASE_ADDR},
 280 };
 281
 282 static iomux_v3_cfg_t const usdhc3_pads[] = {
 283         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 284         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 285         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 286         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 287         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 288         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 289         /* SOM MicroSD Card Detect */
 290         IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 291 };
 292
 293 int board_mmc_getcd(struct mmc *mmc)
 294 {
 295         return 1;
 296 }
 297
 298 int board_mmc_init(bd_t *bis)
 299 {
 300         SETUP_IOMUX_PADS(usdhc3_pads);
 301         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 302         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 303 }
 304 #endif
 305
 306 #ifdef CONFIG_SPL_LOAD_FIT
 307 int board_fit_config_name_match(const char *name)
 308 {
 309         if (is_mx6dq() && !strcmp(name, "imx6q-pico"))
 310                 return 0;
 311         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico"))
 312                 return 0;
 313
 314         return -EINVAL;
 315 }
 316 #endif