board/technexion/pico-imx6/pico-imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2014 O.S. Systems Software LTDA.
   5  *
   6  * Author: Fabio Estevam <festevam@gmail.com>
   7  */
   8
   9 #include <net.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/arch/mxc_hdmi.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/io.h>
  21 #include <linux/sizes.h>
  22 #include <common.h>
  23 #include <miiphy.h>
  24 #include <netdev.h>
  25 #include <phy.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  30         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  31         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  34         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  35
  36 #define ETH_PHY_RESET           IMX_GPIO_NR(1, 26)
  37 #define LVDS0_EN                IMX_GPIO_NR(2, 8)
  38 #define LVDS0_BL_EN             IMX_GPIO_NR(2, 9)
  39
  40 int dram_init(void)
  41 {
  42         gd->ram_size = imx_ddr_size();
  43
  44         return 0;
  45 }
  46
  47 static iomux_v3_cfg_t const uart1_pads[] = {
  48         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  49         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  50 };
  51
  52 static void setup_iomux_uart(void)
  53 {
  54         SETUP_IOMUX_PADS(uart1_pads);
  55 }
  56
  57 static iomux_v3_cfg_t const lvds_pads[] = {
  58         /* lvds */
  59         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  60         IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  61         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
  62         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  63         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  64 };
  65
  66 static iomux_v3_cfg_t const enet_pads[] = {
  67         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  75                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  77                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         /* AR8035 PHY Reset */
  85         IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86 };
  87
  88 static void setup_iomux_enet(void)
  89 {
  90         SETUP_IOMUX_PADS(enet_pads);
  91
  92         /* Reset AR8031 PHY */
  93         gpio_request(ETH_PHY_RESET, "enet_phy_reset");
  94         gpio_direction_output(ETH_PHY_RESET, 0);
  95         udelay(500);
  96         gpio_set_value(ETH_PHY_RESET, 1);
  97 }
  98
  99 #if defined(CONFIG_VIDEO_IPUV3)
 100 static iomux_v3_cfg_t const ft5x06_wvga_pads[] = {
 101         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 102         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
 103         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
 104         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
 105         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
 106         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
 107         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
 108         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
 109         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
 110         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
 111         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
 112         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
 113         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
 114         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
 115         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
 116         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
 117         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
 118         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
 119         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
 120         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
 121         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
 122         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
 123         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
 124         IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
 125         IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
 126         IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
 127         IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
 128         IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
 129         IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
 130         IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
 131         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
 132 };
 133
 134 static void do_enable_hdmi(struct display_info_t const *dev)
 135 {
 136         imx_enable_hdmi_phy();
 137 }
 138
 139 static void enable_lvds(struct display_info_t const *dev)
 140 {
 141         struct iomuxc *iomux = (struct iomuxc *)
 142                                 IOMUXC_BASE_ADDR;
 143
 144         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 145         u32 reg = readl(&iomux->gpr[2]);
 146         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 147         writel(reg, &iomux->gpr[2]);
 148
 149         /* Enable Backlight - use GPIO for Brightness adjustment */
 150         SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
 151         gpio_request(IMX_GPIO_NR(2, 9), "backlight_enable");
 152         gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
 153
 154         gpio_request(IMX_GPIO_NR(2, 8), "brightness");
 155         SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
 156         gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
 157 }
 158
 159 static void enable_ft5x06_wvga(struct display_info_t const *dev)
 160 {
 161         SETUP_IOMUX_PADS(ft5x06_wvga_pads);
 162
 163         gpio_request(IMX_GPIO_NR(2, 10), "parallel_enable");
 164         gpio_request(IMX_GPIO_NR(2, 11), "parallel_brightness");
 165         gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 166         gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 167 }
 168
 169 struct display_info_t const displays[] = {{
 170         .bus    = 1,
 171         .addr   = 0x38,
 172         .pixfmt = IPU_PIX_FMT_RGB24,
 173         .detect = NULL,
 174         .enable = enable_ft5x06_wvga,
 175         .mode   = {
 176                 .name           = "FT5x06-WVGA",
 177                 .refresh        = 60,
 178                 .xres           = 800,
 179                 .yres           = 480,
 180                 .pixclock       = 30303,
 181                 .left_margin    = 45,
 182                 .right_margin   = 210,
 183                 .upper_margin   = 22,
 184                 .lower_margin   = 22,
 185                 .hsync_len      = 1,
 186                 .vsync_len      = 1,
 187                 .sync           = 0,
 188                 .vmode          = FB_VMODE_NONINTERLACED
 189 } }, {
 190         .bus    = -1,
 191         .addr   = 0,
 192         .pixfmt = IPU_PIX_FMT_RGB24,
 193         .detect = NULL,
 194         .enable = enable_lvds,
 195         .mode   = {
 196                 .name           = "hj070na",
 197                 .refresh        = 60,
 198                 .xres           = 1024,
 199                 .yres           = 600,
 200                 .pixclock       = 15385,
 201                 .left_margin    = 220,
 202                 .right_margin   = 40,
 203                 .upper_margin   = 21,
 204                 .lower_margin   = 7,
 205                 .hsync_len      = 60,
 206                 .vsync_len      = 10,
 207                 .sync           = FB_SYNC_EXT,
 208                 .vmode          = FB_VMODE_NONINTERLACED
 209 } }, {
 210         .bus    = -1,
 211         .addr   = 0,
 212         .pixfmt = IPU_PIX_FMT_RGB24,
 213         .detect = detect_hdmi,
 214         .enable = do_enable_hdmi,
 215         .mode   = {
 216                 .name           = "HDMI",
 217                 .refresh        = 60,
 218                 .xres           = 1024,
 219                 .yres           = 768,
 220                 .pixclock       = 15385,
 221                 .left_margin    = 220,
 222                 .right_margin   = 40,
 223                 .upper_margin   = 21,
 224                 .lower_margin   = 7,
 225                 .hsync_len      = 60,
 226                 .vsync_len      = 10,
 227                 .sync           = FB_SYNC_EXT,
 228                 .vmode          = FB_VMODE_NONINTERLACED
 229 } } };
 230 size_t display_count = ARRAY_SIZE(displays);
 231
 232 static void setup_display(void)
 233 {
 234         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 235         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 236         int reg;
 237
 238         /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
 239         SETUP_IOMUX_PADS(lvds_pads);
 240         gpio_request(LVDS0_EN, "lvds0_enable");
 241         gpio_request(LVDS0_BL_EN, "lvds0_bl_enable");
 242         gpio_direction_output(LVDS0_EN, 1);
 243         gpio_direction_output(LVDS0_BL_EN, 1);
 244
 245         enable_ipu_clock();
 246         imx_setup_hdmi();
 247
 248         reg = __raw_readl(&mxc_ccm->CCGR3);
 249         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 250         writel(reg, &mxc_ccm->CCGR3);
 251
 252         /* set LDB0, LDB1 clk select to 011/011 */
 253         reg = readl(&mxc_ccm->cs2cdr);
 254         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 255                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 256         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 257                  | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 258         writel(reg, &mxc_ccm->cs2cdr);
 259
 260         reg = readl(&mxc_ccm->cscmr2);
 261         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 262         writel(reg, &mxc_ccm->cscmr2);
 263
 264         reg = readl(&mxc_ccm->chsccdr);
 265         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 266                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 267         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 268                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 269         writel(reg, &mxc_ccm->chsccdr);
 270
 271          reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 272                 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 273                 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 274                 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 275                 | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
 276                 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 277                 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 278                 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
 279                 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 280         writel(reg, &iomux->gpr[2]);
 281         reg = readl(&iomux->gpr[3]);
 282
 283         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 284                 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 285                 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 286                 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 287
 288         writel(reg, &iomux->gpr[3]);
 289 }
 290 #endif /* CONFIG_VIDEO_IPUV3 */
 291
 292 int board_early_init_f(void)
 293 {
 294         setup_iomux_uart();
 295
 296 #if defined(CONFIG_VIDEO_IPUV3)
 297         setup_display();
 298 #endif
 299
 300         return 0;
 301 }
 302
 303 int board_eth_init(bd_t *bis)
 304 {
 305         setup_iomux_enet();
 306
 307         return cpu_eth_init(bis);
 308 }
 309
 310 int board_phy_config(struct phy_device *phydev)
 311 {
 312         unsigned short val;
 313
 314         /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
 315         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 316         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 317         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 318
 319         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 320         val &= 0xffe7;
 321         val |= 0x18;
 322         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 323
 324         /* introduce tx clock delay */
 325         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 326         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 327         val |= 0x0100;
 328         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 329
 330         if (phydev->drv->config)
 331                 phydev->drv->config(phydev);
 332
 333         return 0;
 334 }
 335
 336 int overwrite_console(void)
 337 {
 338         return 1;
 339 }
 340
 341 int board_late_init(void)
 342 {
 343         if (is_mx6dq())
 344                 env_set("board_rev", "MX6Q");
 345         else
 346                 env_set("board_rev", "MX6DL");
 347
 348         return 0;
 349 }
 350
 351 int board_init(void)
 352 {
 353         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 354
 355         return 0;
 356 }
 357
 358 int checkboard(void)
 359 {
 360         puts("Board: PICO-IMX6\n");
 361
 362         return 0;
 363 }