board/tbs/tbs2910/tbs2910.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
   4  */
   5
   6 #include <init.h>
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/iomux.h>
  10 #include <asm/arch/mx6-pins.h>
  11 #include <asm/global_data.h>
  12 #include <linux/errno.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/boot_mode.h>
  16 #include <asm/mach-imx/video.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc_imx.h>
  19 #include <asm/arch/mxc_hdmi.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/sys_proto.h>
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 int dram_init(void)
  26 {
  27         gd->ram_size = 2048ul * 1024 * 1024;
  28         return 0;
  29 }
  30
  31 #ifdef CONFIG_FSL_ESDHC_IMX
  32 /* set environment device to boot device when booting from SD */
  33 int board_mmc_get_env_dev(int devno)
  34 {
  35         return devno - 1;
  36 }
  37
  38 int board_mmc_get_env_part(int devno)
  39 {
  40         return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
  41 }
  42 #endif /* CONFIG_FSL_ESDHC_IMX */
  43
  44 #ifdef CONFIG_VIDEO_IPUV3
  45 static void do_enable_hdmi(struct display_info_t const *dev)
  46 {
  47         imx_enable_hdmi_phy();
  48 }
  49
  50 struct display_info_t const displays[] = {{
  51         .bus    = -1,
  52         .addr   = 0,
  53         .pixfmt = IPU_PIX_FMT_RGB24,
  54         .detect = detect_hdmi,
  55         .enable = do_enable_hdmi,
  56         .mode   = {
  57                 .name           = "HDMI",
  58                 /* 1024x768@60Hz (VESA)*/
  59                 .refresh        = 60,
  60                 .xres           = 1024,
  61                 .yres           = 768,
  62                 .pixclock       = 15384,
  63                 .left_margin    = 160,
  64                 .right_margin   = 24,
  65                 .upper_margin   = 29,
  66                 .lower_margin   = 3,
  67                 .hsync_len      = 136,
  68                 .vsync_len      = 6,
  69                 .sync           = FB_SYNC_EXT,
  70                 .vmode          = FB_VMODE_NONINTERLACED
  71 } } };
  72 size_t display_count = ARRAY_SIZE(displays);
  73
  74 static void setup_display(void)
  75 {
  76         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  77         int reg;
  78         s32 timeout = 100000;
  79
  80         enable_ipu_clock();
  81         imx_setup_hdmi();
  82
  83         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
  84         reg = readl(&ccm->analog_pll_video);
  85         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
  86         writel(reg, &ccm->analog_pll_video);
  87
  88         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  89         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
  90         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  91         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
  92         writel(reg, &ccm->analog_pll_video);
  93
  94         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  95         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  96
  97         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
  98         writel(reg, &ccm->analog_pll_video);
  99
 100         while (timeout--)
 101                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 102                         break;
 103         if (timeout < 0)
 104                 printf("Warning: video pll lock timeout!\n");
 105
 106         reg = readl(&ccm->analog_pll_video);
 107         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 108         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 109         writel(reg, &ccm->analog_pll_video);
 110
 111         /* gate ipu1_di0_clk */
 112         reg = readl(&ccm->CCGR3);
 113         reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
 114         writel(reg, &ccm->CCGR3);
 115
 116         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 117         reg = readl(&ccm->chsccdr);
 118         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 119                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 120                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 121         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 122                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 123                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 124         writel(reg, &ccm->chsccdr);
 125
 126         /* enable ipu1_di0_clk */
 127         reg = readl(&ccm->CCGR3);
 128         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 129         writel(reg, &ccm->CCGR3);
 130 }
 131 #endif /* CONFIG_VIDEO_IPUV3 */
 132
 133 #ifdef CONFIG_CMD_BMODE
 134 static const struct boot_mode board_boot_modes[] = {
 135         /* 4 bit bus width */
 136         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 137         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 138         /* 8 bit bus width */
 139         {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 140         {NULL,   0},
 141 };
 142 #endif
 143
 144 int board_init(void)
 145 {
 146         /* address of boot parameters */
 147         gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 148
 149 #ifdef CONFIG_VIDEO_IPUV3
 150         setup_display();
 151 #endif
 152 #ifdef CONFIG_CMD_BMODE
 153         add_board_boot_modes(board_boot_modes);
 154 #endif
 155         return 0;
 156 }