board/tbs/tbs2910/tbs2910.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
   4  */
   5
   6 #include <init.h>
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/iomux.h>
  10 #include <asm/arch/mx6-pins.h>
  11 #include <linux/errno.h>
  12 #include <asm/gpio.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15 #include <asm/mach-imx/video.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc_imx.h>
  18 #include <asm/arch/mxc_hdmi.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/sys_proto.h>
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  25         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  26         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  27
  28 static iomux_v3_cfg_t const uart1_pads[] = {
  29         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  30         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  31 };
  32
  33 static iomux_v3_cfg_t const uart2_pads[] = {
  34         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  35         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  36 };
  37
  38 int dram_init(void)
  39 {
  40         gd->ram_size = 2048ul * 1024 * 1024;
  41         return 0;
  42 }
  43
  44 static void setup_iomux_uart(void)
  45 {
  46         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  47         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  48 }
  49
  50 #ifdef CONFIG_FSL_ESDHC_IMX
  51 /* set environment device to boot device when booting from SD */
  52 int board_mmc_get_env_dev(int devno)
  53 {
  54         return devno - 1;
  55 }
  56
  57 int board_mmc_get_env_part(int devno)
  58 {
  59         return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
  60 }
  61 #endif /* CONFIG_FSL_ESDHC_IMX */
  62
  63 #ifdef CONFIG_VIDEO_IPUV3
  64 static void do_enable_hdmi(struct display_info_t const *dev)
  65 {
  66         imx_enable_hdmi_phy();
  67 }
  68
  69 struct display_info_t const displays[] = {{
  70         .bus    = -1,
  71         .addr   = 0,
  72         .pixfmt = IPU_PIX_FMT_RGB24,
  73         .detect = detect_hdmi,
  74         .enable = do_enable_hdmi,
  75         .mode   = {
  76                 .name           = "HDMI",
  77                 /* 1024x768@60Hz (VESA)*/
  78                 .refresh        = 60,
  79                 .xres           = 1024,
  80                 .yres           = 768,
  81                 .pixclock       = 15384,
  82                 .left_margin    = 160,
  83                 .right_margin   = 24,
  84                 .upper_margin   = 29,
  85                 .lower_margin   = 3,
  86                 .hsync_len      = 136,
  87                 .vsync_len      = 6,
  88                 .sync           = FB_SYNC_EXT,
  89                 .vmode          = FB_VMODE_NONINTERLACED
  90 } } };
  91 size_t display_count = ARRAY_SIZE(displays);
  92
  93 static void setup_display(void)
  94 {
  95         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  96         int reg;
  97         s32 timeout = 100000;
  98
  99         enable_ipu_clock();
 100         imx_setup_hdmi();
 101
 102         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 103         reg = readl(&ccm->analog_pll_video);
 104         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 105         writel(reg, &ccm->analog_pll_video);
 106
 107         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 108         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 109         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 110         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 111         writel(reg, &ccm->analog_pll_video);
 112
 113         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 114         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 115
 116         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 117         writel(reg, &ccm->analog_pll_video);
 118
 119         while (timeout--)
 120                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 121                         break;
 122         if (timeout < 0)
 123                 printf("Warning: video pll lock timeout!\n");
 124
 125         reg = readl(&ccm->analog_pll_video);
 126         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 127         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 128         writel(reg, &ccm->analog_pll_video);
 129
 130         /* gate ipu1_di0_clk */
 131         reg = readl(&ccm->CCGR3);
 132         reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
 133         writel(reg, &ccm->CCGR3);
 134
 135         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 136         reg = readl(&ccm->chsccdr);
 137         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 138                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 139                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 140         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 141                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 142                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 143         writel(reg, &ccm->chsccdr);
 144
 145         /* enable ipu1_di0_clk */
 146         reg = readl(&ccm->CCGR3);
 147         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 148         writel(reg, &ccm->CCGR3);
 149 }
 150 #endif /* CONFIG_VIDEO_IPUV3 */
 151
 152 int board_early_init_f(void)
 153 {
 154         setup_iomux_uart();
 155         return 0;
 156 }
 157
 158 #ifdef CONFIG_CMD_BMODE
 159 static const struct boot_mode board_boot_modes[] = {
 160         /* 4 bit bus width */
 161         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 162         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 163         /* 8 bit bus width */
 164         {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 165         {NULL,   0},
 166 };
 167 #endif
 168
 169 int board_init(void)
 170 {
 171         /* address of boot parameters */
 172         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 173
 174 #ifdef CONFIG_VIDEO_IPUV3
 175         setup_display();
 176 #endif
 177 #ifdef CONFIG_CMD_BMODE
 178         add_board_boot_modes(board_boot_modes);
 179 #endif
 180         return 0;
 181 }