1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
12 #include <asm/global_data.h>
13 #include <linux/bitops.h>
15 #include <asm/arcregs.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 #define ARC_PERIPHERAL_BASE 0xF0000000
21 #define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84)
22 #define CGU_ARC_FMEAS_ARC_START BIT(31)
23 #define CGU_ARC_FMEAS_ARC_DONE BIT(30)
24 #define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0)
25 #define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0
26 #define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15
28 #define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000)
30 int mach_cpu_init(void)
35 /* Start frequency measurement */
36 writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC);
40 data = readl(CGU_ARC_FMEAS_ARC);
41 } while (!(data & CGU_ARC_FMEAS_ARC_DONE));
43 /* Amount of reference 100 MHz clocks */
44 rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) &
45 CGU_ARC_FMEAS_ARC_CNT_MASK);
47 /* Amount of CPU clocks */
48 fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) &
49 CGU_ARC_FMEAS_ARC_CNT_MASK);
51 gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000;
56 int board_early_init_r(void)
58 #define EMSDP_PSRAM_BASE 0xf2001000
59 #define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10)
60 #define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14)
61 #define CRE_ENABLE BIT(31)
62 #define CRE_DRIVE_CMD BIT(6)
64 #define PSRAM_RCR_DPD BIT(1)
65 #define PSRAM_RCR_PAGE_MODE BIT(7)
68 * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash,
71 #define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1)
73 // Switch PSRAM controller to command mode
74 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0);
75 // Program Refresh Configuration Register (RCR) for BANK0
76 writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP));
77 // Switch PSRAM controller back to memory mode
78 writel(0, PSRAM_FLASH_CONFIG_REG_0);
81 // Switch PSRAM controller to command mode
82 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
83 // Program Refresh Configuration Register (RCR) for BANK1
84 writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP));
85 // Switch PSRAM controller back to memory mode
86 writel(0, PSRAM_FLASH_CONFIG_REG_1);
88 printf("PSRAM initialized.\n");
93 #define CREG_BASE 0xF0001000
94 #define CREG_BOOT (void *)(CREG_BASE + 0x0FF0)
95 #define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0)
96 #define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8)
98 /* Bits in CREG_BOOT register */
99 #define CREG_BOOT_WP_BIT BIT(8)
101 void reset_cpu(ulong addr)
103 writel(1, CREG_IP_SW_RESET);
105 ; /* loop forever till reset */
108 static int do_emsdp_rom(struct cmd_tbl *cmdtp, int flag, int argc,
111 u32 creg_boot = readl(CREG_BOOT);
113 if (!strcmp(argv[1], "unlock"))
114 creg_boot &= ~CREG_BOOT_WP_BIT;
115 else if (!strcmp(argv[1], "lock"))
116 creg_boot |= CREG_BOOT_WP_BIT;
118 return CMD_RET_USAGE;
120 writel(creg_boot, CREG_BOOT);
122 return CMD_RET_SUCCESS;
125 struct cmd_tbl cmd_emsdp[] = {
126 U_BOOT_CMD_MKENT(rom, 2, 0, do_emsdp_rom, "", ""),
129 static int do_emsdp(struct cmd_tbl *cmdtp, int flag, int argc,
134 c = find_cmd_tbl(argv[1], cmd_emsdp, ARRAY_SIZE(cmd_emsdp));
136 /* Strip off leading 'emsdp' command */
140 if (c == NULL || argc > c->maxargs)
141 return CMD_RET_USAGE;
143 return c->cmd(cmdtp, flag, argc, argv);
147 emsdp, CONFIG_SYS_MAXARGS, 0, do_emsdp,
148 "Synopsys EMSDP specific commands",
149 "rom unlock - Unlock non-volatile memory for writing\n"
150 "emsdp rom lock - Lock non-volatile memory to prevent writing\n"
155 int version = readl(CREG_IP_VERSION);
157 printf("Board: ARC EM Software Development Platform v%d.%d\n",
158 (version >> 16) & 0xff, version & 0xff);