6 #include <asm/arch/clock.h>
7 #include <asm/arch/gpio.h>
9 int sunxi_gmac_initialize(bd_t *bis)
12 struct sunxi_ccm_reg *const ccm =
13 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
15 /* Set up clock gating */
16 #ifndef CONFIG_MACH_SUN6I
17 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
19 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
20 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
25 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
26 CCM_GMAC_CTRL_GPIT_RGMII);
28 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
29 CCM_GMAC_CTRL_GPIT_MII);
33 * In order for the gmac nic to work reliable on the Bananapi, we
34 * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
35 * of the GMAC clk register to 3.
37 #ifdef CONFIG_TARGET_BANANAPI
38 setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
41 #ifndef CONFIG_MACH_SUN6I
42 /* Configure pin mux settings for GMAC */
43 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
45 /* skip unused pins in RGMII mode */
46 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
49 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
50 sunxi_gpio_set_drv(pin, 3);
52 #elif defined CONFIG_RGMII
53 /* Configure sun6i RGMII mode pin mux settings */
54 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
55 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
56 sunxi_gpio_set_drv(pin, 3);
58 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
59 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
60 sunxi_gpio_set_drv(pin, 3);
62 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
63 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
64 sunxi_gpio_set_drv(pin, 3);
66 for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
67 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
68 sunxi_gpio_set_drv(pin, 3);
70 #elif defined CONFIG_GMII
71 /* Configure sun6i GMII mode pin mux settings */
72 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
73 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
74 sunxi_gpio_set_drv(pin, 2);
77 /* Configure sun6i MII mode pin mux settings */
78 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
79 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
80 for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
81 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
82 for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
83 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
84 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
85 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
86 for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
87 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
91 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
92 #elif defined CONFIG_GMII
93 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
95 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);