1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
22 #include <generic-phy.h>
23 #include <phy-sun4i-usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/display.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/spl.h>
32 #include <linux/delay.h>
33 #include <u-boot/crc.h>
35 #include <asm/armv7.h>
39 #include <u-boot/crc.h>
40 #include <env_internal.h>
41 #include <linux/libfdt.h>
42 #include <fdt_support.h>
47 #include <asm/setup.h>
49 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
50 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
51 int soft_i2c_gpio_sda;
52 int soft_i2c_gpio_scl;
54 static int soft_i2c_board_init(void)
58 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
59 if (soft_i2c_gpio_sda < 0) {
60 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
61 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
62 return soft_i2c_gpio_sda;
64 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
66 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
67 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
71 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
72 if (soft_i2c_gpio_scl < 0) {
73 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
74 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
75 return soft_i2c_gpio_scl;
77 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
79 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
80 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
87 static int soft_i2c_board_init(void) { return 0; }
90 DECLARE_GLOBAL_DATA_PTR;
92 void i2c_init_board(void)
94 #ifdef CONFIG_I2C0_ENABLE
95 #if defined(CONFIG_MACH_SUN4I) || \
96 defined(CONFIG_MACH_SUN5I) || \
97 defined(CONFIG_MACH_SUN7I) || \
98 defined(CONFIG_MACH_SUN8I_R40)
99 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
100 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
101 clock_twi_onoff(0, 1);
102 #elif defined(CONFIG_MACH_SUN6I)
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
105 clock_twi_onoff(0, 1);
106 #elif defined(CONFIG_MACH_SUN8I_V3S)
107 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
109 clock_twi_onoff(0, 1);
110 #elif defined(CONFIG_MACH_SUN8I)
111 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
112 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
113 clock_twi_onoff(0, 1);
114 #elif defined(CONFIG_MACH_SUN50I)
115 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
117 clock_twi_onoff(0, 1);
121 #ifdef CONFIG_I2C1_ENABLE
122 #if defined(CONFIG_MACH_SUN4I) || \
123 defined(CONFIG_MACH_SUN7I) || \
124 defined(CONFIG_MACH_SUN8I_R40)
125 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
126 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
127 clock_twi_onoff(1, 1);
128 #elif defined(CONFIG_MACH_SUN5I)
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
131 clock_twi_onoff(1, 1);
132 #elif defined(CONFIG_MACH_SUN6I)
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
134 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
135 clock_twi_onoff(1, 1);
136 #elif defined(CONFIG_MACH_SUN8I)
137 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
139 clock_twi_onoff(1, 1);
140 #elif defined(CONFIG_MACH_SUN50I)
141 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
142 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
143 clock_twi_onoff(1, 1);
147 #ifdef CONFIG_I2C2_ENABLE
148 #if defined(CONFIG_MACH_SUN4I) || \
149 defined(CONFIG_MACH_SUN7I) || \
150 defined(CONFIG_MACH_SUN8I_R40)
151 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
152 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
153 clock_twi_onoff(2, 1);
154 #elif defined(CONFIG_MACH_SUN5I)
155 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
156 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
157 clock_twi_onoff(2, 1);
158 #elif defined(CONFIG_MACH_SUN6I)
159 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
160 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
161 clock_twi_onoff(2, 1);
162 #elif defined(CONFIG_MACH_SUN8I)
163 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
164 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
165 clock_twi_onoff(2, 1);
166 #elif defined(CONFIG_MACH_SUN50I)
167 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
168 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
169 clock_twi_onoff(2, 1);
173 #ifdef CONFIG_I2C3_ENABLE
174 #if defined(CONFIG_MACH_SUN6I)
175 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
176 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
177 clock_twi_onoff(3, 1);
178 #elif defined(CONFIG_MACH_SUN7I) || \
179 defined(CONFIG_MACH_SUN8I_R40)
180 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
181 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
182 clock_twi_onoff(3, 1);
186 #ifdef CONFIG_I2C4_ENABLE
187 #if defined(CONFIG_MACH_SUN7I) || \
188 defined(CONFIG_MACH_SUN8I_R40)
189 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
190 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
191 clock_twi_onoff(4, 1);
195 #ifdef CONFIG_R_I2C_ENABLE
196 #ifdef CONFIG_MACH_SUN50I
197 clock_twi_onoff(5, 1);
198 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
199 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
200 #elif CONFIG_MACH_SUN50I_H616
201 clock_twi_onoff(5, 1);
202 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
203 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
205 clock_twi_onoff(5, 1);
206 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
207 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
212 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
213 enum env_location env_get_location(enum env_operation op, int prio)
229 static void mmc_pinmux_setup(int sdc);
232 /* add board specific code here */
235 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
237 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
240 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
241 debug("id_pfr1: 0x%08x\n", id_pfr1);
242 /* Generic Timer Extension available? */
243 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
246 debug("Setting CNTFRQ\n");
249 * CNTFRQ is a secure register, so we will crash if we try to
250 * write this from the non-secure world (read is OK, though).
251 * In case some bootcode has already set the correct value,
252 * we avoid the risk of writing to it.
254 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
255 if (freq != COUNTER_FREQUENCY) {
256 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
257 freq, COUNTER_FREQUENCY);
258 #ifdef CONFIG_NON_SECURE
259 printf("arch timer frequency is wrong, but cannot adjust it\n");
261 asm volatile("mcr p15, 0, %0, c14, c0, 0"
262 : : "r"(COUNTER_FREQUENCY));
266 #endif /* !CONFIG_ARM64 */
268 ret = axp_gpio_init();
272 /* strcmp() would look better, but doesn't get optimised away. */
273 if (CONFIG_SATAPWR[0]) {
274 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
275 if (satapwr_pin >= 0) {
276 gpio_request(satapwr_pin, "satapwr");
277 gpio_direction_output(satapwr_pin, 1);
280 * Give the attached SATA device time to power-up
281 * to avoid link timeouts
287 if (CONFIG_MACPWR[0]) {
288 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
289 if (macpwr_pin >= 0) {
290 gpio_request(macpwr_pin, "macpwr");
291 gpio_direction_output(macpwr_pin, 1);
297 * Temporary workaround for enabling I2C clocks until proper sunxi DM
298 * clk, reset and pinctrl drivers land.
305 * Temporary workaround for enabling MMC clocks until a sunxi DM
306 * pinctrl driver lands.
308 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
309 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
310 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
312 #endif /* CONFIG_DM_MMC */
314 /* Uses dm gpio code so do this here and not in i2c_init_board() */
315 return soft_i2c_board_init();
319 * On older SoCs the SPL is actually at address zero, so using NULL as
320 * an error value does not work.
322 #define INVALID_SPL_HEADER ((void *)~0UL)
324 static struct boot_file_head * get_spl_header(uint8_t req_version)
326 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
327 uint8_t spl_header_version = spl->spl_signature[3];
329 /* Is there really the SPL header (still) there? */
330 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
331 return INVALID_SPL_HEADER;
333 if (spl_header_version < req_version) {
334 printf("sunxi SPL version mismatch: expected %u, got %u\n",
335 req_version, spl_header_version);
336 return INVALID_SPL_HEADER;
342 static const char *get_spl_dt_name(void)
344 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
346 /* Check if there is a DT name stored in the SPL header. */
347 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
348 return (char *)spl + spl->dt_name_offset;
355 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
357 if (spl == INVALID_SPL_HEADER)
358 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
361 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
363 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
364 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
369 #if defined(CONFIG_NAND_SUNXI)
370 static void nand_pinmux_setup(void)
374 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
375 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
377 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
378 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
379 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
381 /* sun4i / sun7i do have a PC23, but it is not used for nand,
382 * only sun7i has a PC24 */
383 #ifdef CONFIG_MACH_SUN7I
384 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
388 static void nand_clock_setup(void)
390 struct sunxi_ccm_reg *const ccm =
391 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
393 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
394 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
395 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
396 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
398 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
401 void board_nand_init(void)
405 #ifndef CONFIG_SPL_BUILD
412 static void mmc_pinmux_setup(int sdc)
415 __maybe_unused int pins;
420 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
421 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
422 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
423 sunxi_gpio_set_drv(pin, 2);
428 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
430 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
431 defined(CONFIG_MACH_SUN8I_R40)
432 if (pins == SUNXI_GPIO_H) {
433 /* SDC1: PH22-PH-27 */
434 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
435 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
436 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
437 sunxi_gpio_set_drv(pin, 2);
441 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
442 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
443 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
444 sunxi_gpio_set_drv(pin, 2);
447 #elif defined(CONFIG_MACH_SUN5I)
449 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
450 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
451 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
452 sunxi_gpio_set_drv(pin, 2);
454 #elif defined(CONFIG_MACH_SUN6I)
456 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
457 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
458 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
459 sunxi_gpio_set_drv(pin, 2);
461 #elif defined(CONFIG_MACH_SUN8I)
462 if (pins == SUNXI_GPIO_D) {
464 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
465 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
466 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
467 sunxi_gpio_set_drv(pin, 2);
471 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
472 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
473 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
474 sunxi_gpio_set_drv(pin, 2);
481 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
483 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
485 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
486 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
487 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
488 sunxi_gpio_set_drv(pin, 2);
490 #elif defined(CONFIG_MACH_SUN5I)
491 if (pins == SUNXI_GPIO_E) {
493 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
494 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
495 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
496 sunxi_gpio_set_drv(pin, 2);
500 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
501 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
502 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
503 sunxi_gpio_set_drv(pin, 2);
506 #elif defined(CONFIG_MACH_SUN6I)
507 if (pins == SUNXI_GPIO_A) {
509 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
510 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
511 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
512 sunxi_gpio_set_drv(pin, 2);
515 /* SDC2: PC6-PC15, PC24 */
516 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
517 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
518 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
519 sunxi_gpio_set_drv(pin, 2);
522 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
523 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
524 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
526 #elif defined(CONFIG_MACH_SUN8I_R40)
527 /* SDC2: PC6-PC15, PC24 */
528 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
529 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
530 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
531 sunxi_gpio_set_drv(pin, 2);
534 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
535 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
536 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
537 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
538 /* SDC2: PC5-PC6, PC8-PC16 */
539 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
540 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
541 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
542 sunxi_gpio_set_drv(pin, 2);
545 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
546 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
547 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
548 sunxi_gpio_set_drv(pin, 2);
550 #elif defined(CONFIG_MACH_SUN50I_H6)
552 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
553 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
554 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
555 sunxi_gpio_set_drv(pin, 2);
557 #elif defined(CONFIG_MACH_SUN9I)
559 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
560 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
561 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
562 sunxi_gpio_set_drv(pin, 2);
568 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
570 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
571 defined(CONFIG_MACH_SUN8I_R40)
573 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
574 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
575 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
576 sunxi_gpio_set_drv(pin, 2);
578 #elif defined(CONFIG_MACH_SUN6I)
579 if (pins == SUNXI_GPIO_A) {
581 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
582 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
583 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
584 sunxi_gpio_set_drv(pin, 2);
587 /* SDC3: PC6-PC15, PC24 */
588 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
589 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
590 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
591 sunxi_gpio_set_drv(pin, 2);
594 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
595 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
596 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
602 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
607 int board_mmc_init(struct bd_info *bis)
609 __maybe_unused struct mmc *mmc0, *mmc1;
611 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
612 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
616 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
617 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
618 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
627 #ifdef CONFIG_SPL_BUILD
629 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
631 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
633 if (spl == INVALID_SPL_HEADER)
636 /* Promote the header version for U-Boot proper, if needed. */
637 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
638 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
640 spl->dram_size = dram_size >> 20;
643 void sunxi_board_init(void)
645 int power_failed = 0;
647 #ifdef CONFIG_SY8106A_POWER
648 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
651 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
652 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
653 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
654 power_failed = axp_init();
656 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
657 defined CONFIG_AXP818_POWER
658 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
660 #if !defined(CONFIG_AXP305_POWER)
661 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
662 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
664 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
665 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
667 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
668 defined CONFIG_AXP818_POWER
669 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
672 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
673 defined CONFIG_AXP818_POWER
674 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
676 #if !defined(CONFIG_AXP305_POWER)
677 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
679 #if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
680 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
682 #ifdef CONFIG_AXP209_POWER
683 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
686 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
687 defined(CONFIG_AXP818_POWER)
688 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
689 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
690 #if !defined CONFIG_AXP809_POWER
691 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
692 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
694 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
695 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
696 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
699 #ifdef CONFIG_AXP818_POWER
700 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
701 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
702 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
705 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
706 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
710 gd->ram_size = sunxi_dram_init();
711 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
715 sunxi_spl_store_dram_size(gd->ram_size);
718 * Only clock up the CPU to full speed if we are reasonably
719 * assured it's being powered with suitable core voltage
722 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
724 printf("Failed to set core voltage! Can't set CPU frequency\n");
728 #ifdef CONFIG_USB_GADGET
729 int g_dnl_board_usb_cable_connected(void)
735 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
737 pr_err("%s: Cannot find USB device\n", __func__);
741 ret = generic_phy_get_by_name(dev, "usb", &phy);
743 pr_err("failed to get %s USB PHY\n", dev->name);
747 ret = generic_phy_init(&phy);
749 pr_debug("failed to init %s USB PHY\n", dev->name);
753 ret = sun4i_usb_phy_vbus_detect(&phy);
755 pr_err("A charger is plugged into the OTG\n");
763 #ifdef CONFIG_SERIAL_TAG
764 void get_board_serial(struct tag_serialnr *serialnr)
767 unsigned long long serial;
769 serial_string = env_get("serial#");
772 serial = simple_strtoull(serial_string, NULL, 16);
774 serialnr->high = (unsigned int) (serial >> 32);
775 serialnr->low = (unsigned int) (serial & 0xffffffff);
784 * Check the SPL header for the "sunxi" variant. If found: parse values
785 * that might have been passed by the loader ("fel" utility), and update
786 * the environment accordingly.
788 static void parse_spl_header(const uint32_t spl_addr)
790 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
792 if (spl == INVALID_SPL_HEADER)
795 if (!spl->fel_script_address)
798 if (spl->fel_uEnv_length != 0) {
800 * data is expected in uEnv.txt compatible format, so "env
801 * import -t" the string(s) at fel_script_address right away.
803 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
804 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
807 /* otherwise assume .scr format (mkimage-type script) */
808 env_set_hex("fel_scriptaddr", spl->fel_script_address);
811 static bool get_unique_sid(unsigned int *sid)
813 if (sunxi_get_sid(sid) != 0)
820 * The single words 1 - 3 of the SID have quite a few bits
821 * which are the same on many models, so we take a crc32
822 * of all 3 words, to get a more unique value.
824 * Note we only do this on newer SoCs as we cannot change
825 * the algorithm on older SoCs since those have been using
826 * fixed mac-addresses based on only using word 3 for a
827 * long time and changing a fixed mac-address with an
828 * u-boot update is not good.
830 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
831 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
832 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
833 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
836 /* Ensure the NIC specific bytes of the mac are not all 0 */
837 if ((sid[3] & 0xffffff) == 0)
844 * Note this function gets called multiple times.
845 * It must not make any changes to env variables which already exist.
847 static void setup_environment(const void *fdt)
849 char serial_string[17] = { 0 };
855 if (!get_unique_sid(sid))
858 for (i = 0; i < 4; i++) {
859 sprintf(ethaddr, "ethernet%d", i);
860 if (!fdt_get_alias(fdt, ethaddr))
864 strcpy(ethaddr, "ethaddr");
866 sprintf(ethaddr, "eth%daddr", i);
868 if (env_get(ethaddr))
871 /* Non OUI / registered MAC address */
872 mac_addr[0] = (i << 4) | 0x02;
873 mac_addr[1] = (sid[0] >> 0) & 0xff;
874 mac_addr[2] = (sid[3] >> 24) & 0xff;
875 mac_addr[3] = (sid[3] >> 16) & 0xff;
876 mac_addr[4] = (sid[3] >> 8) & 0xff;
877 mac_addr[5] = (sid[3] >> 0) & 0xff;
879 eth_env_set_enetaddr(ethaddr, mac_addr);
882 if (!env_get("serial#")) {
883 snprintf(serial_string, sizeof(serial_string),
884 "%08x%08x", sid[0], sid[3]);
886 env_set("serial#", serial_string);
890 int misc_init_r(void)
892 const char *spl_dt_name;
895 env_set("fel_booted", NULL);
896 env_set("fel_scriptaddr", NULL);
897 env_set("mmc_bootdev", NULL);
899 boot = sunxi_get_boot_device();
900 /* determine if we are running in FEL mode */
901 if (boot == BOOT_DEVICE_BOARD) {
902 env_set("fel_booted", "1");
903 parse_spl_header(SPL_ADDR);
904 /* or if we booted from MMC, and which one */
905 } else if (boot == BOOT_DEVICE_MMC1) {
906 env_set("mmc_bootdev", "0");
907 } else if (boot == BOOT_DEVICE_MMC2) {
908 env_set("mmc_bootdev", "1");
911 /* Set fdtfile to match the FIT configuration chosen in SPL. */
912 spl_dt_name = get_spl_dt_name();
914 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
917 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
918 env_set("fdtfile", str);
921 setup_environment(gd->fdt_blob);
926 int board_late_init(void)
928 #ifdef CONFIG_USB_ETHER
935 static void bluetooth_dt_fixup(void *blob)
937 /* Some devices ship with a Bluetooth controller default address.
938 * Set a valid address through the device tree.
940 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
944 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
947 if (eth_env_get_enetaddr("bdaddr", tmp)) {
948 /* Convert between the binary formats of the corresponding stacks */
949 for (i = 0; i < ETH_ALEN; ++i)
950 bdaddr[i] = tmp[ETH_ALEN - i - 1];
952 if (!get_unique_sid(sid))
955 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
956 bdaddr[1] = (sid[3] >> 8) & 0xff;
957 bdaddr[2] = (sid[3] >> 16) & 0xff;
958 bdaddr[3] = (sid[3] >> 24) & 0xff;
959 bdaddr[4] = (sid[0] >> 0) & 0xff;
963 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
964 "local-bd-address", bdaddr, ETH_ALEN, 1);
967 int ft_board_setup(void *blob, struct bd_info *bd)
969 int __maybe_unused r;
972 * Call setup_environment again in case the boot fdt has
973 * ethernet aliases the u-boot copy does not have.
975 setup_environment(blob);
977 bluetooth_dt_fixup(blob);
979 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
980 r = sunxi_simplefb_setup(blob);
987 #ifdef CONFIG_SPL_LOAD_FIT
989 static void set_spl_dt_name(const char *name)
991 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
993 if (spl == INVALID_SPL_HEADER)
996 /* Promote the header version for U-Boot proper, if needed. */
997 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
998 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
1000 strcpy((char *)&spl->string_pool, name);
1001 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
1004 int board_fit_config_name_match(const char *name)
1006 const char *best_dt_name = get_spl_dt_name();
1009 #ifdef CONFIG_DEFAULT_DEVICE_TREE
1010 if (best_dt_name == NULL)
1011 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
1014 if (best_dt_name == NULL) {
1015 /* No DT name was provided, so accept the first config. */
1018 #ifdef CONFIG_PINE64_DT_SELECTION
1019 if (strstr(best_dt_name, "-pine64-plus")) {
1020 /* Differentiate the Pine A64 boards by their DRAM size. */
1021 if ((gd->ram_size == 512 * 1024 * 1024))
1022 best_dt_name = "sun50i-a64-pine64";
1025 #ifdef CONFIG_PINEPHONE_DT_SELECTION
1026 if (strstr(best_dt_name, "-pinephone")) {
1027 /* Differentiate the PinePhone revisions by GPIO inputs. */
1028 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
1029 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
1030 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
1033 /* PL6 is pulled low by the modem on v1.2. */
1034 if (gpio_get_value(SUNXI_GPL(6)) == 0)
1035 best_dt_name = "sun50i-a64-pinephone-1.2";
1037 best_dt_name = "sun50i-a64-pinephone-1.1";
1039 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
1040 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
1041 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
1045 ret = strcmp(name, best_dt_name);
1048 * If one of the FIT configurations matches the most accurate DT name,
1049 * update the SPL header to provide that DT name to U-Boot proper.
1052 set_spl_dt_name(best_dt_name);