1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
22 #include <generic-phy.h>
23 #include <phy-sun4i-usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/display.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/spl.h>
32 #include <asm/global_data.h>
33 #include <linux/delay.h>
34 #include <u-boot/crc.h>
36 #include <asm/armv7.h>
40 #include <u-boot/crc.h>
41 #include <env_internal.h>
42 #include <linux/libfdt.h>
43 #include <fdt_support.h>
48 #include <asm/setup.h>
50 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
51 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
52 int soft_i2c_gpio_sda;
53 int soft_i2c_gpio_scl;
55 static int soft_i2c_board_init(void)
59 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
60 if (soft_i2c_gpio_sda < 0) {
61 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
63 return soft_i2c_gpio_sda;
65 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
67 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
72 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
73 if (soft_i2c_gpio_scl < 0) {
74 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
75 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
76 return soft_i2c_gpio_scl;
78 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
80 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
81 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
88 static int soft_i2c_board_init(void) { return 0; }
91 DECLARE_GLOBAL_DATA_PTR;
93 void i2c_init_board(void)
95 #ifdef CONFIG_I2C0_ENABLE
96 #if defined(CONFIG_MACH_SUN4I) || \
97 defined(CONFIG_MACH_SUN5I) || \
98 defined(CONFIG_MACH_SUN7I) || \
99 defined(CONFIG_MACH_SUN8I_R40)
100 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
102 clock_twi_onoff(0, 1);
103 #elif defined(CONFIG_MACH_SUN6I)
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
106 clock_twi_onoff(0, 1);
107 #elif defined(CONFIG_MACH_SUN8I_V3S)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
110 clock_twi_onoff(0, 1);
111 #elif defined(CONFIG_MACH_SUN8I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
114 clock_twi_onoff(0, 1);
115 #elif defined(CONFIG_MACH_SUN50I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
118 clock_twi_onoff(0, 1);
122 #ifdef CONFIG_I2C1_ENABLE
123 #if defined(CONFIG_MACH_SUN4I) || \
124 defined(CONFIG_MACH_SUN7I) || \
125 defined(CONFIG_MACH_SUN8I_R40)
126 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
127 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
128 clock_twi_onoff(1, 1);
129 #elif defined(CONFIG_MACH_SUN5I)
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
132 clock_twi_onoff(1, 1);
133 #elif defined(CONFIG_MACH_SUN6I)
134 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
135 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
136 clock_twi_onoff(1, 1);
137 #elif defined(CONFIG_MACH_SUN8I)
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
140 clock_twi_onoff(1, 1);
141 #elif defined(CONFIG_MACH_SUN50I)
142 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
143 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
144 clock_twi_onoff(1, 1);
148 #ifdef CONFIG_I2C2_ENABLE
149 #if defined(CONFIG_MACH_SUN4I) || \
150 defined(CONFIG_MACH_SUN7I) || \
151 defined(CONFIG_MACH_SUN8I_R40)
152 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
153 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
154 clock_twi_onoff(2, 1);
155 #elif defined(CONFIG_MACH_SUN5I)
156 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
157 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
158 clock_twi_onoff(2, 1);
159 #elif defined(CONFIG_MACH_SUN6I)
160 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
161 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
162 clock_twi_onoff(2, 1);
163 #elif defined(CONFIG_MACH_SUN8I)
164 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
165 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
166 clock_twi_onoff(2, 1);
167 #elif defined(CONFIG_MACH_SUN50I)
168 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
169 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
170 clock_twi_onoff(2, 1);
174 #ifdef CONFIG_I2C3_ENABLE
175 #if defined(CONFIG_MACH_SUN6I)
176 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
177 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
178 clock_twi_onoff(3, 1);
179 #elif defined(CONFIG_MACH_SUN7I) || \
180 defined(CONFIG_MACH_SUN8I_R40)
181 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
182 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
183 clock_twi_onoff(3, 1);
187 #ifdef CONFIG_I2C4_ENABLE
188 #if defined(CONFIG_MACH_SUN7I) || \
189 defined(CONFIG_MACH_SUN8I_R40)
190 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
191 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
192 clock_twi_onoff(4, 1);
196 #ifdef CONFIG_R_I2C_ENABLE
197 #ifdef CONFIG_MACH_SUN50I
198 clock_twi_onoff(5, 1);
199 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
200 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
201 #elif CONFIG_MACH_SUN50I_H616
202 clock_twi_onoff(5, 1);
203 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
204 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
206 clock_twi_onoff(5, 1);
207 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
208 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
213 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
214 enum env_location env_get_location(enum env_operation op, int prio)
230 static void mmc_pinmux_setup(int sdc);
233 /* add board specific code here */
236 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
238 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
241 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
242 debug("id_pfr1: 0x%08x\n", id_pfr1);
243 /* Generic Timer Extension available? */
244 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
247 debug("Setting CNTFRQ\n");
250 * CNTFRQ is a secure register, so we will crash if we try to
251 * write this from the non-secure world (read is OK, though).
252 * In case some bootcode has already set the correct value,
253 * we avoid the risk of writing to it.
255 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
256 if (freq != COUNTER_FREQUENCY) {
257 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
258 freq, COUNTER_FREQUENCY);
259 #ifdef CONFIG_NON_SECURE
260 printf("arch timer frequency is wrong, but cannot adjust it\n");
262 asm volatile("mcr p15, 0, %0, c14, c0, 0"
263 : : "r"(COUNTER_FREQUENCY));
267 #endif /* !CONFIG_ARM64 */
269 ret = axp_gpio_init();
273 /* strcmp() would look better, but doesn't get optimised away. */
274 if (CONFIG_SATAPWR[0]) {
275 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
276 if (satapwr_pin >= 0) {
277 gpio_request(satapwr_pin, "satapwr");
278 gpio_direction_output(satapwr_pin, 1);
281 * Give the attached SATA device time to power-up
282 * to avoid link timeouts
288 if (CONFIG_MACPWR[0]) {
289 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
290 if (macpwr_pin >= 0) {
291 gpio_request(macpwr_pin, "macpwr");
292 gpio_direction_output(macpwr_pin, 1);
296 #if CONFIG_IS_ENABLED(DM_I2C)
298 * Temporary workaround for enabling I2C clocks until proper sunxi DM
299 * clk, reset and pinctrl drivers land.
306 * Temporary workaround for enabling MMC clocks until a sunxi DM
307 * pinctrl driver lands.
309 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
310 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
311 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
313 #endif /* CONFIG_DM_MMC */
315 /* Uses dm gpio code so do this here and not in i2c_init_board() */
316 return soft_i2c_board_init();
320 * On older SoCs the SPL is actually at address zero, so using NULL as
321 * an error value does not work.
323 #define INVALID_SPL_HEADER ((void *)~0UL)
325 static struct boot_file_head * get_spl_header(uint8_t req_version)
327 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
328 uint8_t spl_header_version = spl->spl_signature[3];
330 /* Is there really the SPL header (still) there? */
331 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
332 return INVALID_SPL_HEADER;
334 if (spl_header_version < req_version) {
335 printf("sunxi SPL version mismatch: expected %u, got %u\n",
336 req_version, spl_header_version);
337 return INVALID_SPL_HEADER;
343 static const char *get_spl_dt_name(void)
345 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
347 /* Check if there is a DT name stored in the SPL header. */
348 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
349 return (char *)spl + spl->dt_name_offset;
356 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
358 if (spl == INVALID_SPL_HEADER)
359 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
362 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
364 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
365 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
370 #if defined(CONFIG_NAND_SUNXI)
371 static void nand_pinmux_setup(void)
375 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
376 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
378 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
379 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
380 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
382 /* sun4i / sun7i do have a PC23, but it is not used for nand,
383 * only sun7i has a PC24 */
384 #ifdef CONFIG_MACH_SUN7I
385 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
389 static void nand_clock_setup(void)
391 struct sunxi_ccm_reg *const ccm =
392 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
394 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
395 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
396 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
397 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
399 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
402 void board_nand_init(void)
406 #ifndef CONFIG_SPL_BUILD
413 static void mmc_pinmux_setup(int sdc)
416 __maybe_unused int pins;
421 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
422 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
423 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
424 sunxi_gpio_set_drv(pin, 2);
429 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
431 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
432 defined(CONFIG_MACH_SUN8I_R40)
433 if (pins == SUNXI_GPIO_H) {
434 /* SDC1: PH22-PH-27 */
435 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
436 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
437 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
438 sunxi_gpio_set_drv(pin, 2);
442 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
443 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
444 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
445 sunxi_gpio_set_drv(pin, 2);
448 #elif defined(CONFIG_MACH_SUN5I)
450 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
451 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
452 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
453 sunxi_gpio_set_drv(pin, 2);
455 #elif defined(CONFIG_MACH_SUN6I)
457 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
458 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
459 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
460 sunxi_gpio_set_drv(pin, 2);
462 #elif defined(CONFIG_MACH_SUN8I)
463 if (pins == SUNXI_GPIO_D) {
465 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
466 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
467 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
468 sunxi_gpio_set_drv(pin, 2);
472 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
473 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
474 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
475 sunxi_gpio_set_drv(pin, 2);
482 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
484 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
486 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
487 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
488 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
489 sunxi_gpio_set_drv(pin, 2);
491 #elif defined(CONFIG_MACH_SUN5I)
492 if (pins == SUNXI_GPIO_E) {
494 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
495 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
496 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
497 sunxi_gpio_set_drv(pin, 2);
501 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
502 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
503 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
504 sunxi_gpio_set_drv(pin, 2);
507 #elif defined(CONFIG_MACH_SUN6I)
508 if (pins == SUNXI_GPIO_A) {
510 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
511 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
512 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
513 sunxi_gpio_set_drv(pin, 2);
516 /* SDC2: PC6-PC15, PC24 */
517 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
518 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
519 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
520 sunxi_gpio_set_drv(pin, 2);
523 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
524 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
525 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
527 #elif defined(CONFIG_MACH_SUN8I_R40)
528 /* SDC2: PC6-PC15, PC24 */
529 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
530 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
531 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
532 sunxi_gpio_set_drv(pin, 2);
535 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
536 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
537 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
538 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
539 /* SDC2: PC5-PC6, PC8-PC16 */
540 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
541 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
542 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
543 sunxi_gpio_set_drv(pin, 2);
546 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
547 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
548 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
549 sunxi_gpio_set_drv(pin, 2);
551 #elif defined(CONFIG_MACH_SUN50I_H6)
553 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
554 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
555 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
556 sunxi_gpio_set_drv(pin, 2);
558 #elif defined(CONFIG_MACH_SUN9I)
560 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
561 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
562 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
563 sunxi_gpio_set_drv(pin, 2);
569 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
571 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
572 defined(CONFIG_MACH_SUN8I_R40)
574 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
575 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
576 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
577 sunxi_gpio_set_drv(pin, 2);
579 #elif defined(CONFIG_MACH_SUN6I)
580 if (pins == SUNXI_GPIO_A) {
582 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
583 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
584 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
585 sunxi_gpio_set_drv(pin, 2);
588 /* SDC3: PC6-PC15, PC24 */
589 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
590 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
591 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
592 sunxi_gpio_set_drv(pin, 2);
595 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
596 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
597 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
603 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
608 int board_mmc_init(struct bd_info *bis)
610 __maybe_unused struct mmc *mmc0, *mmc1;
612 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
613 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
617 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
618 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
619 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
628 #ifdef CONFIG_SPL_BUILD
630 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
632 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
634 if (spl == INVALID_SPL_HEADER)
637 /* Promote the header version for U-Boot proper, if needed. */
638 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
639 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
641 spl->dram_size = dram_size >> 20;
644 void sunxi_board_init(void)
646 int power_failed = 0;
648 #ifdef CONFIG_SY8106A_POWER
649 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
652 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
653 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
654 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
655 power_failed = axp_init();
657 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
658 defined CONFIG_AXP818_POWER
659 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
661 #if !defined(CONFIG_AXP305_POWER)
662 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
663 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
665 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
666 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
668 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
669 defined CONFIG_AXP818_POWER
670 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
673 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
674 defined CONFIG_AXP818_POWER
675 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
677 #if !defined(CONFIG_AXP305_POWER)
678 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
680 #if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
681 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
683 #ifdef CONFIG_AXP209_POWER
684 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
687 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
688 defined(CONFIG_AXP818_POWER)
689 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
690 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
691 #if !defined CONFIG_AXP809_POWER
692 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
693 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
695 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
696 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
697 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
700 #ifdef CONFIG_AXP818_POWER
701 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
702 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
703 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
706 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
707 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
711 gd->ram_size = sunxi_dram_init();
712 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
716 sunxi_spl_store_dram_size(gd->ram_size);
719 * Only clock up the CPU to full speed if we are reasonably
720 * assured it's being powered with suitable core voltage
723 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
725 printf("Failed to set core voltage! Can't set CPU frequency\n");
729 #ifdef CONFIG_USB_GADGET
730 int g_dnl_board_usb_cable_connected(void)
736 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
738 pr_err("%s: Cannot find USB device\n", __func__);
742 ret = generic_phy_get_by_name(dev, "usb", &phy);
744 pr_err("failed to get %s USB PHY\n", dev->name);
748 ret = generic_phy_init(&phy);
750 pr_debug("failed to init %s USB PHY\n", dev->name);
754 ret = sun4i_usb_phy_vbus_detect(&phy);
756 pr_err("A charger is plugged into the OTG\n");
764 #ifdef CONFIG_SERIAL_TAG
765 void get_board_serial(struct tag_serialnr *serialnr)
768 unsigned long long serial;
770 serial_string = env_get("serial#");
773 serial = simple_strtoull(serial_string, NULL, 16);
775 serialnr->high = (unsigned int) (serial >> 32);
776 serialnr->low = (unsigned int) (serial & 0xffffffff);
785 * Check the SPL header for the "sunxi" variant. If found: parse values
786 * that might have been passed by the loader ("fel" utility), and update
787 * the environment accordingly.
789 static void parse_spl_header(const uint32_t spl_addr)
791 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
793 if (spl == INVALID_SPL_HEADER)
796 if (!spl->fel_script_address)
799 if (spl->fel_uEnv_length != 0) {
801 * data is expected in uEnv.txt compatible format, so "env
802 * import -t" the string(s) at fel_script_address right away.
804 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
805 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
808 /* otherwise assume .scr format (mkimage-type script) */
809 env_set_hex("fel_scriptaddr", spl->fel_script_address);
812 static bool get_unique_sid(unsigned int *sid)
814 if (sunxi_get_sid(sid) != 0)
821 * The single words 1 - 3 of the SID have quite a few bits
822 * which are the same on many models, so we take a crc32
823 * of all 3 words, to get a more unique value.
825 * Note we only do this on newer SoCs as we cannot change
826 * the algorithm on older SoCs since those have been using
827 * fixed mac-addresses based on only using word 3 for a
828 * long time and changing a fixed mac-address with an
829 * u-boot update is not good.
831 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
832 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
833 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
834 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
837 /* Ensure the NIC specific bytes of the mac are not all 0 */
838 if ((sid[3] & 0xffffff) == 0)
845 * Note this function gets called multiple times.
846 * It must not make any changes to env variables which already exist.
848 static void setup_environment(const void *fdt)
850 char serial_string[17] = { 0 };
856 if (!get_unique_sid(sid))
859 for (i = 0; i < 4; i++) {
860 sprintf(ethaddr, "ethernet%d", i);
861 if (!fdt_get_alias(fdt, ethaddr))
865 strcpy(ethaddr, "ethaddr");
867 sprintf(ethaddr, "eth%daddr", i);
869 if (env_get(ethaddr))
872 /* Non OUI / registered MAC address */
873 mac_addr[0] = (i << 4) | 0x02;
874 mac_addr[1] = (sid[0] >> 0) & 0xff;
875 mac_addr[2] = (sid[3] >> 24) & 0xff;
876 mac_addr[3] = (sid[3] >> 16) & 0xff;
877 mac_addr[4] = (sid[3] >> 8) & 0xff;
878 mac_addr[5] = (sid[3] >> 0) & 0xff;
880 eth_env_set_enetaddr(ethaddr, mac_addr);
883 if (!env_get("serial#")) {
884 snprintf(serial_string, sizeof(serial_string),
885 "%08x%08x", sid[0], sid[3]);
887 env_set("serial#", serial_string);
891 int misc_init_r(void)
893 const char *spl_dt_name;
896 env_set("fel_booted", NULL);
897 env_set("fel_scriptaddr", NULL);
898 env_set("mmc_bootdev", NULL);
900 boot = sunxi_get_boot_device();
901 /* determine if we are running in FEL mode */
902 if (boot == BOOT_DEVICE_BOARD) {
903 env_set("fel_booted", "1");
904 parse_spl_header(SPL_ADDR);
905 /* or if we booted from MMC, and which one */
906 } else if (boot == BOOT_DEVICE_MMC1) {
907 env_set("mmc_bootdev", "0");
908 } else if (boot == BOOT_DEVICE_MMC2) {
909 env_set("mmc_bootdev", "1");
912 /* Set fdtfile to match the FIT configuration chosen in SPL. */
913 spl_dt_name = get_spl_dt_name();
915 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
918 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
919 env_set("fdtfile", str);
922 setup_environment(gd->fdt_blob);
927 int board_late_init(void)
929 #ifdef CONFIG_USB_ETHER
936 static void bluetooth_dt_fixup(void *blob)
938 /* Some devices ship with a Bluetooth controller default address.
939 * Set a valid address through the device tree.
941 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
945 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
948 if (eth_env_get_enetaddr("bdaddr", tmp)) {
949 /* Convert between the binary formats of the corresponding stacks */
950 for (i = 0; i < ETH_ALEN; ++i)
951 bdaddr[i] = tmp[ETH_ALEN - i - 1];
953 if (!get_unique_sid(sid))
956 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
957 bdaddr[1] = (sid[3] >> 8) & 0xff;
958 bdaddr[2] = (sid[3] >> 16) & 0xff;
959 bdaddr[3] = (sid[3] >> 24) & 0xff;
960 bdaddr[4] = (sid[0] >> 0) & 0xff;
964 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
965 "local-bd-address", bdaddr, ETH_ALEN, 1);
968 int ft_board_setup(void *blob, struct bd_info *bd)
970 int __maybe_unused r;
973 * Call setup_environment again in case the boot fdt has
974 * ethernet aliases the u-boot copy does not have.
976 setup_environment(blob);
978 bluetooth_dt_fixup(blob);
980 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
981 r = sunxi_simplefb_setup(blob);
988 #ifdef CONFIG_SPL_LOAD_FIT
990 static void set_spl_dt_name(const char *name)
992 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
994 if (spl == INVALID_SPL_HEADER)
997 /* Promote the header version for U-Boot proper, if needed. */
998 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
999 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
1001 strcpy((char *)&spl->string_pool, name);
1002 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
1005 int board_fit_config_name_match(const char *name)
1007 const char *best_dt_name = get_spl_dt_name();
1010 #ifdef CONFIG_DEFAULT_DEVICE_TREE
1011 if (best_dt_name == NULL)
1012 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
1015 if (best_dt_name == NULL) {
1016 /* No DT name was provided, so accept the first config. */
1019 #ifdef CONFIG_PINE64_DT_SELECTION
1020 if (strstr(best_dt_name, "-pine64-plus")) {
1021 /* Differentiate the Pine A64 boards by their DRAM size. */
1022 if ((gd->ram_size == 512 * 1024 * 1024))
1023 best_dt_name = "sun50i-a64-pine64";
1026 #ifdef CONFIG_PINEPHONE_DT_SELECTION
1027 if (strstr(best_dt_name, "-pinephone")) {
1028 /* Differentiate the PinePhone revisions by GPIO inputs. */
1029 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
1030 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
1031 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
1034 /* PL6 is pulled low by the modem on v1.2. */
1035 if (gpio_get_value(SUNXI_GPL(6)) == 0)
1036 best_dt_name = "sun50i-a64-pinephone-1.2";
1038 best_dt_name = "sun50i-a64-pinephone-1.1";
1040 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
1041 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
1042 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
1046 ret = strcmp(name, best_dt_name);
1049 * If one of the FIT configurations matches the most accurate DT name,
1050 * update the SPL header to provide that DT name to U-Boot proper.
1053 set_spl_dt_name(best_dt_name);