1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
22 #include <generic-phy.h>
23 #include <phy-sun4i-usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/display.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/spl.h>
32 #include <linux/delay.h>
33 #include <u-boot/crc.h>
35 #include <asm/armv7.h>
39 #include <u-boot/crc.h>
40 #include <env_internal.h>
41 #include <linux/libfdt.h>
42 #include <fdt_support.h>
47 #include <asm/setup.h>
49 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
50 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
51 int soft_i2c_gpio_sda;
52 int soft_i2c_gpio_scl;
54 static int soft_i2c_board_init(void)
58 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
59 if (soft_i2c_gpio_sda < 0) {
60 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
61 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
62 return soft_i2c_gpio_sda;
64 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
66 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
67 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
71 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
72 if (soft_i2c_gpio_scl < 0) {
73 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
74 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
75 return soft_i2c_gpio_scl;
77 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
79 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
80 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
87 static int soft_i2c_board_init(void) { return 0; }
90 DECLARE_GLOBAL_DATA_PTR;
92 void i2c_init_board(void)
94 #ifdef CONFIG_I2C0_ENABLE
95 #if defined(CONFIG_MACH_SUN4I) || \
96 defined(CONFIG_MACH_SUN5I) || \
97 defined(CONFIG_MACH_SUN7I) || \
98 defined(CONFIG_MACH_SUN8I_R40)
99 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
100 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
101 clock_twi_onoff(0, 1);
102 #elif defined(CONFIG_MACH_SUN6I)
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
105 clock_twi_onoff(0, 1);
106 #elif defined(CONFIG_MACH_SUN8I_V3S)
107 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
109 clock_twi_onoff(0, 1);
110 #elif defined(CONFIG_MACH_SUN8I)
111 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
112 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
113 clock_twi_onoff(0, 1);
114 #elif defined(CONFIG_MACH_SUN50I)
115 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
117 clock_twi_onoff(0, 1);
121 #ifdef CONFIG_I2C1_ENABLE
122 #if defined(CONFIG_MACH_SUN4I) || \
123 defined(CONFIG_MACH_SUN7I) || \
124 defined(CONFIG_MACH_SUN8I_R40)
125 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
126 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
127 clock_twi_onoff(1, 1);
128 #elif defined(CONFIG_MACH_SUN5I)
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
131 clock_twi_onoff(1, 1);
132 #elif defined(CONFIG_MACH_SUN6I)
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
134 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
135 clock_twi_onoff(1, 1);
136 #elif defined(CONFIG_MACH_SUN8I)
137 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
139 clock_twi_onoff(1, 1);
140 #elif defined(CONFIG_MACH_SUN50I)
141 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
142 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
143 clock_twi_onoff(1, 1);
147 #ifdef CONFIG_I2C2_ENABLE
148 #if defined(CONFIG_MACH_SUN4I) || \
149 defined(CONFIG_MACH_SUN7I) || \
150 defined(CONFIG_MACH_SUN8I_R40)
151 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
152 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
153 clock_twi_onoff(2, 1);
154 #elif defined(CONFIG_MACH_SUN5I)
155 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
156 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
157 clock_twi_onoff(2, 1);
158 #elif defined(CONFIG_MACH_SUN6I)
159 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
160 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
161 clock_twi_onoff(2, 1);
162 #elif defined(CONFIG_MACH_SUN8I)
163 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
164 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
165 clock_twi_onoff(2, 1);
166 #elif defined(CONFIG_MACH_SUN50I)
167 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
168 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
169 clock_twi_onoff(2, 1);
173 #ifdef CONFIG_I2C3_ENABLE
174 #if defined(CONFIG_MACH_SUN6I)
175 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
176 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
177 clock_twi_onoff(3, 1);
178 #elif defined(CONFIG_MACH_SUN7I) || \
179 defined(CONFIG_MACH_SUN8I_R40)
180 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
181 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
182 clock_twi_onoff(3, 1);
186 #ifdef CONFIG_I2C4_ENABLE
187 #if defined(CONFIG_MACH_SUN7I) || \
188 defined(CONFIG_MACH_SUN8I_R40)
189 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
190 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
191 clock_twi_onoff(4, 1);
195 #ifdef CONFIG_R_I2C_ENABLE
196 #ifdef CONFIG_MACH_SUN50I
197 clock_twi_onoff(5, 1);
198 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
199 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
201 clock_twi_onoff(5, 1);
202 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
203 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
208 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
209 enum env_location env_get_location(enum env_operation op, int prio)
225 static void mmc_pinmux_setup(int sdc);
228 /* add board specific code here */
231 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
233 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
236 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
237 debug("id_pfr1: 0x%08x\n", id_pfr1);
238 /* Generic Timer Extension available? */
239 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
242 debug("Setting CNTFRQ\n");
245 * CNTFRQ is a secure register, so we will crash if we try to
246 * write this from the non-secure world (read is OK, though).
247 * In case some bootcode has already set the correct value,
248 * we avoid the risk of writing to it.
250 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
251 if (freq != COUNTER_FREQUENCY) {
252 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
253 freq, COUNTER_FREQUENCY);
254 #ifdef CONFIG_NON_SECURE
255 printf("arch timer frequency is wrong, but cannot adjust it\n");
257 asm volatile("mcr p15, 0, %0, c14, c0, 0"
258 : : "r"(COUNTER_FREQUENCY));
262 #endif /* !CONFIG_ARM64 */
264 ret = axp_gpio_init();
268 #ifdef CONFIG_SATAPWR
269 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
270 gpio_request(satapwr_pin, "satapwr");
271 gpio_direction_output(satapwr_pin, 1);
272 /* Give attached sata device time to power-up to avoid link timeouts */
276 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
277 gpio_request(macpwr_pin, "macpwr");
278 gpio_direction_output(macpwr_pin, 1);
283 * Temporary workaround for enabling I2C clocks until proper sunxi DM
284 * clk, reset and pinctrl drivers land.
291 * Temporary workaround for enabling MMC clocks until a sunxi DM
292 * pinctrl driver lands.
294 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
295 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
296 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
298 #endif /* CONFIG_DM_MMC */
300 /* Uses dm gpio code so do this here and not in i2c_init_board() */
301 return soft_i2c_board_init();
305 * On older SoCs the SPL is actually at address zero, so using NULL as
306 * an error value does not work.
308 #define INVALID_SPL_HEADER ((void *)~0UL)
310 static struct boot_file_head * get_spl_header(uint8_t req_version)
312 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
313 uint8_t spl_header_version = spl->spl_signature[3];
315 /* Is there really the SPL header (still) there? */
316 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
317 return INVALID_SPL_HEADER;
319 if (spl_header_version < req_version) {
320 printf("sunxi SPL version mismatch: expected %u, got %u\n",
321 req_version, spl_header_version);
322 return INVALID_SPL_HEADER;
328 static const char *get_spl_dt_name(void)
330 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
332 /* Check if there is a DT name stored in the SPL header. */
333 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
334 return (char *)spl + spl->dt_name_offset;
341 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
343 if (spl == INVALID_SPL_HEADER)
344 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
347 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
349 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
350 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
355 #if defined(CONFIG_NAND_SUNXI)
356 static void nand_pinmux_setup(void)
360 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
361 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
363 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
364 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
365 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
367 /* sun4i / sun7i do have a PC23, but it is not used for nand,
368 * only sun7i has a PC24 */
369 #ifdef CONFIG_MACH_SUN7I
370 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
374 static void nand_clock_setup(void)
376 struct sunxi_ccm_reg *const ccm =
377 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
379 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
380 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
381 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
382 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
384 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
387 void board_nand_init(void)
391 #ifndef CONFIG_SPL_BUILD
398 static void mmc_pinmux_setup(int sdc)
401 __maybe_unused int pins;
406 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
407 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
408 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
409 sunxi_gpio_set_drv(pin, 2);
414 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
416 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
417 defined(CONFIG_MACH_SUN8I_R40)
418 if (pins == SUNXI_GPIO_H) {
419 /* SDC1: PH22-PH-27 */
420 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
421 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
422 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
423 sunxi_gpio_set_drv(pin, 2);
427 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
428 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
429 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
430 sunxi_gpio_set_drv(pin, 2);
433 #elif defined(CONFIG_MACH_SUN5I)
435 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
436 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
437 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
438 sunxi_gpio_set_drv(pin, 2);
440 #elif defined(CONFIG_MACH_SUN6I)
442 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
443 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
444 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
445 sunxi_gpio_set_drv(pin, 2);
447 #elif defined(CONFIG_MACH_SUN8I)
448 if (pins == SUNXI_GPIO_D) {
450 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
451 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
452 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
453 sunxi_gpio_set_drv(pin, 2);
457 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
458 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
459 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
460 sunxi_gpio_set_drv(pin, 2);
467 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
469 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
471 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
472 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
473 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
474 sunxi_gpio_set_drv(pin, 2);
476 #elif defined(CONFIG_MACH_SUN5I)
477 if (pins == SUNXI_GPIO_E) {
479 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
480 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
481 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
482 sunxi_gpio_set_drv(pin, 2);
486 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
487 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
488 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
489 sunxi_gpio_set_drv(pin, 2);
492 #elif defined(CONFIG_MACH_SUN6I)
493 if (pins == SUNXI_GPIO_A) {
495 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
496 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
497 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
498 sunxi_gpio_set_drv(pin, 2);
501 /* SDC2: PC6-PC15, PC24 */
502 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
503 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
504 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
505 sunxi_gpio_set_drv(pin, 2);
508 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
509 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
510 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
512 #elif defined(CONFIG_MACH_SUN8I_R40)
513 /* SDC2: PC6-PC15, PC24 */
514 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
515 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
516 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
517 sunxi_gpio_set_drv(pin, 2);
520 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
521 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
522 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
523 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
524 /* SDC2: PC5-PC6, PC8-PC16 */
525 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
526 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
527 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
528 sunxi_gpio_set_drv(pin, 2);
531 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
532 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
533 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
534 sunxi_gpio_set_drv(pin, 2);
536 #elif defined(CONFIG_MACH_SUN50I_H6)
538 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
539 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
540 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
541 sunxi_gpio_set_drv(pin, 2);
543 #elif defined(CONFIG_MACH_SUN9I)
545 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
546 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
547 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
548 sunxi_gpio_set_drv(pin, 2);
554 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
556 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
557 defined(CONFIG_MACH_SUN8I_R40)
559 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
560 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
561 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
562 sunxi_gpio_set_drv(pin, 2);
564 #elif defined(CONFIG_MACH_SUN6I)
565 if (pins == SUNXI_GPIO_A) {
567 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
568 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
569 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
570 sunxi_gpio_set_drv(pin, 2);
573 /* SDC3: PC6-PC15, PC24 */
574 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
575 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
576 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
577 sunxi_gpio_set_drv(pin, 2);
580 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
581 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
582 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
588 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
593 int board_mmc_init(struct bd_info *bis)
595 __maybe_unused struct mmc *mmc0, *mmc1;
597 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
598 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
602 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
603 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
604 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
613 #ifdef CONFIG_SPL_BUILD
615 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
617 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
619 if (spl == INVALID_SPL_HEADER)
622 /* Promote the header version for U-Boot proper, if needed. */
623 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
624 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
626 spl->dram_size = dram_size >> 20;
629 void sunxi_board_init(void)
631 int power_failed = 0;
633 #ifdef CONFIG_SY8106A_POWER
634 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
637 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
638 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
639 defined CONFIG_AXP818_POWER
640 power_failed = axp_init();
642 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
643 defined CONFIG_AXP818_POWER
644 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
646 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
647 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
648 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
649 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
651 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
652 defined CONFIG_AXP818_POWER
653 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
656 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
657 defined CONFIG_AXP818_POWER
658 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
660 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
661 #if !defined(CONFIG_AXP152_POWER)
662 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
664 #ifdef CONFIG_AXP209_POWER
665 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
668 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
669 defined(CONFIG_AXP818_POWER)
670 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
671 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
672 #if !defined CONFIG_AXP809_POWER
673 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
674 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
676 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
677 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
678 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
681 #ifdef CONFIG_AXP818_POWER
682 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
683 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
684 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
687 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
688 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
692 gd->ram_size = sunxi_dram_init();
693 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
697 sunxi_spl_store_dram_size(gd->ram_size);
700 * Only clock up the CPU to full speed if we are reasonably
701 * assured it's being powered with suitable core voltage
704 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
706 printf("Failed to set core voltage! Can't set CPU frequency\n");
710 #ifdef CONFIG_USB_GADGET
711 int g_dnl_board_usb_cable_connected(void)
717 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
719 pr_err("%s: Cannot find USB device\n", __func__);
723 ret = generic_phy_get_by_name(dev, "usb", &phy);
725 pr_err("failed to get %s USB PHY\n", dev->name);
729 ret = generic_phy_init(&phy);
731 pr_debug("failed to init %s USB PHY\n", dev->name);
735 ret = sun4i_usb_phy_vbus_detect(&phy);
737 pr_err("A charger is plugged into the OTG\n");
745 #ifdef CONFIG_SERIAL_TAG
746 void get_board_serial(struct tag_serialnr *serialnr)
749 unsigned long long serial;
751 serial_string = env_get("serial#");
754 serial = simple_strtoull(serial_string, NULL, 16);
756 serialnr->high = (unsigned int) (serial >> 32);
757 serialnr->low = (unsigned int) (serial & 0xffffffff);
766 * Check the SPL header for the "sunxi" variant. If found: parse values
767 * that might have been passed by the loader ("fel" utility), and update
768 * the environment accordingly.
770 static void parse_spl_header(const uint32_t spl_addr)
772 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
774 if (spl == INVALID_SPL_HEADER)
777 if (!spl->fel_script_address)
780 if (spl->fel_uEnv_length != 0) {
782 * data is expected in uEnv.txt compatible format, so "env
783 * import -t" the string(s) at fel_script_address right away.
785 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
786 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
789 /* otherwise assume .scr format (mkimage-type script) */
790 env_set_hex("fel_scriptaddr", spl->fel_script_address);
793 static bool get_unique_sid(unsigned int *sid)
795 if (sunxi_get_sid(sid) != 0)
802 * The single words 1 - 3 of the SID have quite a few bits
803 * which are the same on many models, so we take a crc32
804 * of all 3 words, to get a more unique value.
806 * Note we only do this on newer SoCs as we cannot change
807 * the algorithm on older SoCs since those have been using
808 * fixed mac-addresses based on only using word 3 for a
809 * long time and changing a fixed mac-address with an
810 * u-boot update is not good.
812 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
813 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
814 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
815 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
818 /* Ensure the NIC specific bytes of the mac are not all 0 */
819 if ((sid[3] & 0xffffff) == 0)
826 * Note this function gets called multiple times.
827 * It must not make any changes to env variables which already exist.
829 static void setup_environment(const void *fdt)
831 char serial_string[17] = { 0 };
837 if (!get_unique_sid(sid))
840 for (i = 0; i < 4; i++) {
841 sprintf(ethaddr, "ethernet%d", i);
842 if (!fdt_get_alias(fdt, ethaddr))
846 strcpy(ethaddr, "ethaddr");
848 sprintf(ethaddr, "eth%daddr", i);
850 if (env_get(ethaddr))
853 /* Non OUI / registered MAC address */
854 mac_addr[0] = (i << 4) | 0x02;
855 mac_addr[1] = (sid[0] >> 0) & 0xff;
856 mac_addr[2] = (sid[3] >> 24) & 0xff;
857 mac_addr[3] = (sid[3] >> 16) & 0xff;
858 mac_addr[4] = (sid[3] >> 8) & 0xff;
859 mac_addr[5] = (sid[3] >> 0) & 0xff;
861 eth_env_set_enetaddr(ethaddr, mac_addr);
864 if (!env_get("serial#")) {
865 snprintf(serial_string, sizeof(serial_string),
866 "%08x%08x", sid[0], sid[3]);
868 env_set("serial#", serial_string);
872 int misc_init_r(void)
874 const char *spl_dt_name;
877 env_set("fel_booted", NULL);
878 env_set("fel_scriptaddr", NULL);
879 env_set("mmc_bootdev", NULL);
881 boot = sunxi_get_boot_device();
882 /* determine if we are running in FEL mode */
883 if (boot == BOOT_DEVICE_BOARD) {
884 env_set("fel_booted", "1");
885 parse_spl_header(SPL_ADDR);
886 /* or if we booted from MMC, and which one */
887 } else if (boot == BOOT_DEVICE_MMC1) {
888 env_set("mmc_bootdev", "0");
889 } else if (boot == BOOT_DEVICE_MMC2) {
890 env_set("mmc_bootdev", "1");
893 /* Set fdtfile to match the FIT configuration chosen in SPL. */
894 spl_dt_name = get_spl_dt_name();
896 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
899 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
900 env_set("fdtfile", str);
903 setup_environment(gd->fdt_blob);
908 int board_late_init(void)
910 #ifdef CONFIG_USB_ETHER
917 static void bluetooth_dt_fixup(void *blob)
919 /* Some devices ship with a Bluetooth controller default address.
920 * Set a valid address through the device tree.
922 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
926 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
929 if (eth_env_get_enetaddr("bdaddr", tmp)) {
930 /* Convert between the binary formats of the corresponding stacks */
931 for (i = 0; i < ETH_ALEN; ++i)
932 bdaddr[i] = tmp[ETH_ALEN - i - 1];
934 if (!get_unique_sid(sid))
937 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
938 bdaddr[1] = (sid[3] >> 8) & 0xff;
939 bdaddr[2] = (sid[3] >> 16) & 0xff;
940 bdaddr[3] = (sid[3] >> 24) & 0xff;
941 bdaddr[4] = (sid[0] >> 0) & 0xff;
945 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
946 "local-bd-address", bdaddr, ETH_ALEN, 1);
949 int ft_board_setup(void *blob, struct bd_info *bd)
951 int __maybe_unused r;
954 * Call setup_environment again in case the boot fdt has
955 * ethernet aliases the u-boot copy does not have.
957 setup_environment(blob);
959 bluetooth_dt_fixup(blob);
961 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
962 r = sunxi_simplefb_setup(blob);
969 #ifdef CONFIG_SPL_LOAD_FIT
971 static void set_spl_dt_name(const char *name)
973 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
975 if (spl == INVALID_SPL_HEADER)
978 /* Promote the header version for U-Boot proper, if needed. */
979 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
980 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
982 strcpy((char *)&spl->string_pool, name);
983 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
986 int board_fit_config_name_match(const char *name)
988 const char *best_dt_name = get_spl_dt_name();
991 #ifdef CONFIG_DEFAULT_DEVICE_TREE
992 if (best_dt_name == NULL)
993 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
996 if (best_dt_name == NULL) {
997 /* No DT name was provided, so accept the first config. */
1000 #ifdef CONFIG_PINE64_DT_SELECTION
1001 if (strstr(best_dt_name, "-pine64-plus")) {
1002 /* Differentiate the Pine A64 boards by their DRAM size. */
1003 if ((gd->ram_size == 512 * 1024 * 1024))
1004 best_dt_name = "sun50i-a64-pine64";
1007 #ifdef CONFIG_PINEPHONE_DT_SELECTION
1008 if (strstr(best_dt_name, "-pinephone")) {
1009 /* Differentiate the PinePhone revisions by GPIO inputs. */
1010 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
1011 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
1012 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
1015 /* PL6 is pulled low by the modem on v1.2. */
1016 if (gpio_get_value(SUNXI_GPL(6)) == 0)
1017 best_dt_name = "sun50i-a64-pinephone-1.2";
1019 best_dt_name = "sun50i-a64-pinephone-1.1";
1021 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
1022 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
1023 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
1027 ret = strcmp(name, best_dt_name);
1030 * If one of the FIT configurations matches the most accurate DT name,
1031 * update the SPL header to provide that DT name to U-Boot proper.
1034 set_spl_dt_name(best_dt_name);