1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
22 #include <generic-phy.h>
23 #include <phy-sun4i-usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/display.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/spl.h>
32 #include <asm/global_data.h>
33 #include <linux/delay.h>
34 #include <u-boot/crc.h>
36 #include <asm/armv7.h>
40 #include <u-boot/crc.h>
41 #include <env_internal.h>
42 #include <linux/libfdt.h>
43 #include <fdt_support.h>
48 #include <asm/setup.h>
49 #include <status_led.h>
51 #if defined(CONFIG_VIDEO_LCD_PANEL_I2C)
52 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
53 int soft_i2c_gpio_sda;
54 int soft_i2c_gpio_scl;
56 static int soft_i2c_board_init(void)
60 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
61 if (soft_i2c_gpio_sda < 0) {
62 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
63 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
64 return soft_i2c_gpio_sda;
66 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
68 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
69 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
73 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
74 if (soft_i2c_gpio_scl < 0) {
75 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
76 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
77 return soft_i2c_gpio_scl;
79 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
81 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
82 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
89 static int soft_i2c_board_init(void) { return 0; }
92 DECLARE_GLOBAL_DATA_PTR;
94 void i2c_init_board(void)
96 #ifdef CONFIG_I2C0_ENABLE
97 #if defined(CONFIG_MACH_SUN4I) || \
98 defined(CONFIG_MACH_SUN5I) || \
99 defined(CONFIG_MACH_SUN7I) || \
100 defined(CONFIG_MACH_SUN8I_R40)
101 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
102 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
103 clock_twi_onoff(0, 1);
104 #elif defined(CONFIG_MACH_SUN6I)
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
106 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
107 clock_twi_onoff(0, 1);
108 #elif defined(CONFIG_MACH_SUN8I_V3S)
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
111 clock_twi_onoff(0, 1);
112 #elif defined(CONFIG_MACH_SUN8I)
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
114 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
115 clock_twi_onoff(0, 1);
116 #elif defined(CONFIG_MACH_SUN50I)
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
118 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
119 clock_twi_onoff(0, 1);
123 #ifdef CONFIG_I2C1_ENABLE
124 #if defined(CONFIG_MACH_SUN4I) || \
125 defined(CONFIG_MACH_SUN7I) || \
126 defined(CONFIG_MACH_SUN8I_R40)
127 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
128 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
129 clock_twi_onoff(1, 1);
130 #elif defined(CONFIG_MACH_SUN5I)
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
132 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
133 clock_twi_onoff(1, 1);
134 #elif defined(CONFIG_MACH_SUN6I)
135 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
136 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
137 clock_twi_onoff(1, 1);
138 #elif defined(CONFIG_MACH_SUN8I)
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
140 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
141 clock_twi_onoff(1, 1);
142 #elif defined(CONFIG_MACH_SUN50I)
143 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
144 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
145 clock_twi_onoff(1, 1);
149 #ifdef CONFIG_I2C2_ENABLE
150 #if defined(CONFIG_MACH_SUN4I) || \
151 defined(CONFIG_MACH_SUN7I) || \
152 defined(CONFIG_MACH_SUN8I_R40)
153 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
154 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
155 clock_twi_onoff(2, 1);
156 #elif defined(CONFIG_MACH_SUN5I)
157 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
158 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
159 clock_twi_onoff(2, 1);
160 #elif defined(CONFIG_MACH_SUN6I)
161 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
162 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
163 clock_twi_onoff(2, 1);
164 #elif defined(CONFIG_MACH_SUN8I)
165 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
166 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
167 clock_twi_onoff(2, 1);
168 #elif defined(CONFIG_MACH_SUN50I)
169 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
170 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
171 clock_twi_onoff(2, 1);
175 #ifdef CONFIG_I2C3_ENABLE
176 #if defined(CONFIG_MACH_SUN6I)
177 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
178 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
179 clock_twi_onoff(3, 1);
180 #elif defined(CONFIG_MACH_SUN7I) || \
181 defined(CONFIG_MACH_SUN8I_R40)
182 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
183 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
184 clock_twi_onoff(3, 1);
188 #ifdef CONFIG_I2C4_ENABLE
189 #if defined(CONFIG_MACH_SUN7I) || \
190 defined(CONFIG_MACH_SUN8I_R40)
191 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
192 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
193 clock_twi_onoff(4, 1);
197 #ifdef CONFIG_R_I2C_ENABLE
198 #ifdef CONFIG_MACH_SUN50I
199 clock_twi_onoff(5, 1);
200 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
201 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
202 #elif CONFIG_MACH_SUN50I_H616
203 clock_twi_onoff(5, 1);
204 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
205 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
207 clock_twi_onoff(5, 1);
208 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
209 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
214 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
215 enum env_location env_get_location(enum env_operation op, int prio)
231 static void mmc_pinmux_setup(int sdc);
234 /* add board specific code here */
237 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
239 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
242 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
243 debug("id_pfr1: 0x%08x\n", id_pfr1);
244 /* Generic Timer Extension available? */
245 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
248 debug("Setting CNTFRQ\n");
251 * CNTFRQ is a secure register, so we will crash if we try to
252 * write this from the non-secure world (read is OK, though).
253 * In case some bootcode has already set the correct value,
254 * we avoid the risk of writing to it.
256 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
257 if (freq != COUNTER_FREQUENCY) {
258 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
259 freq, COUNTER_FREQUENCY);
260 #ifdef CONFIG_NON_SECURE
261 printf("arch timer frequency is wrong, but cannot adjust it\n");
263 asm volatile("mcr p15, 0, %0, c14, c0, 0"
264 : : "r"(COUNTER_FREQUENCY));
268 #endif /* !CONFIG_ARM64 */
270 ret = axp_gpio_init();
274 /* strcmp() would look better, but doesn't get optimised away. */
275 if (CONFIG_SATAPWR[0]) {
276 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
277 if (satapwr_pin >= 0) {
278 gpio_request(satapwr_pin, "satapwr");
279 gpio_direction_output(satapwr_pin, 1);
282 * Give the attached SATA device time to power-up
283 * to avoid link timeouts
289 if (CONFIG_MACPWR[0]) {
290 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
291 if (macpwr_pin >= 0) {
292 gpio_request(macpwr_pin, "macpwr");
293 gpio_direction_output(macpwr_pin, 1);
297 #if CONFIG_IS_ENABLED(DM_I2C)
299 * Temporary workaround for enabling I2C clocks until proper sunxi DM
300 * clk, reset and pinctrl drivers land.
307 * Temporary workaround for enabling MMC clocks until a sunxi DM
308 * pinctrl driver lands.
310 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
311 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
312 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
314 #endif /* CONFIG_DM_MMC */
316 /* Uses dm gpio code so do this here and not in i2c_init_board() */
317 return soft_i2c_board_init();
321 * On older SoCs the SPL is actually at address zero, so using NULL as
322 * an error value does not work.
324 #define INVALID_SPL_HEADER ((void *)~0UL)
326 static struct boot_file_head * get_spl_header(uint8_t req_version)
328 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
329 uint8_t spl_header_version = spl->spl_signature[3];
331 /* Is there really the SPL header (still) there? */
332 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
333 return INVALID_SPL_HEADER;
335 if (spl_header_version < req_version) {
336 printf("sunxi SPL version mismatch: expected %u, got %u\n",
337 req_version, spl_header_version);
338 return INVALID_SPL_HEADER;
344 static const char *get_spl_dt_name(void)
346 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
348 /* Check if there is a DT name stored in the SPL header. */
349 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
350 return (char *)spl + spl->dt_name_offset;
357 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
359 if (spl == INVALID_SPL_HEADER)
360 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
363 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
365 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
366 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
371 #if defined(CONFIG_NAND_SUNXI)
372 static void nand_pinmux_setup(void)
376 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
377 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
379 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
380 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
381 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
383 /* sun4i / sun7i do have a PC23, but it is not used for nand,
384 * only sun7i has a PC24 */
385 #ifdef CONFIG_MACH_SUN7I
386 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
390 static void nand_clock_setup(void)
392 struct sunxi_ccm_reg *const ccm =
393 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
395 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
396 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
397 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
398 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
400 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
403 void board_nand_init(void)
407 #ifndef CONFIG_SPL_BUILD
414 static void mmc_pinmux_setup(int sdc)
421 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
422 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
423 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
424 sunxi_gpio_set_drv(pin, 2);
429 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
430 defined(CONFIG_MACH_SUN8I_R40)
431 if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
432 /* SDC1: PH22-PH-27 */
433 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
434 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
435 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
436 sunxi_gpio_set_drv(pin, 2);
440 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
441 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
442 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
443 sunxi_gpio_set_drv(pin, 2);
446 #elif defined(CONFIG_MACH_SUN5I)
448 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
449 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
450 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
451 sunxi_gpio_set_drv(pin, 2);
453 #elif defined(CONFIG_MACH_SUN6I)
455 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
456 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
457 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
458 sunxi_gpio_set_drv(pin, 2);
460 #elif defined(CONFIG_MACH_SUN8I)
462 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
463 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
464 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
465 sunxi_gpio_set_drv(pin, 2);
471 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
473 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
474 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
475 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
476 sunxi_gpio_set_drv(pin, 2);
478 #elif defined(CONFIG_MACH_SUN5I)
480 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
481 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
482 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
483 sunxi_gpio_set_drv(pin, 2);
485 #elif defined(CONFIG_MACH_SUN6I)
486 /* SDC2: PC6-PC15, PC24 */
487 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
488 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
489 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
490 sunxi_gpio_set_drv(pin, 2);
493 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
494 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
495 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
496 #elif defined(CONFIG_MACH_SUN8I_R40)
497 /* SDC2: PC6-PC15, PC24 */
498 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
499 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
500 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
501 sunxi_gpio_set_drv(pin, 2);
504 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
505 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
506 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
507 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
508 /* SDC2: PC5-PC6, PC8-PC16 */
509 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
510 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
511 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
512 sunxi_gpio_set_drv(pin, 2);
515 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
516 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
517 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
518 sunxi_gpio_set_drv(pin, 2);
520 #elif defined(CONFIG_MACH_SUN50I_H6)
522 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
523 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
524 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
525 sunxi_gpio_set_drv(pin, 2);
527 #elif defined(CONFIG_MACH_SUN50I_H616)
528 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
529 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
530 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
532 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
534 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
535 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
536 sunxi_gpio_set_drv(pin, 3);
538 #elif defined(CONFIG_MACH_SUN9I)
540 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
541 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
542 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
543 sunxi_gpio_set_drv(pin, 2);
546 puts("ERROR: No pinmux setup defined for MMC2!\n");
551 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
552 defined(CONFIG_MACH_SUN8I_R40)
554 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
555 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
556 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
557 sunxi_gpio_set_drv(pin, 2);
559 #elif defined(CONFIG_MACH_SUN6I)
560 /* SDC3: PC6-PC15, PC24 */
561 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
562 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
563 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
564 sunxi_gpio_set_drv(pin, 2);
567 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
568 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
569 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
574 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
579 int board_mmc_init(struct bd_info *bis)
581 __maybe_unused struct mmc *mmc0, *mmc1;
583 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
584 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
588 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
589 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
590 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
598 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
599 int mmc_get_env_dev(void)
601 switch (sunxi_get_boot_device()) {
602 case BOOT_DEVICE_MMC1:
604 case BOOT_DEVICE_MMC2:
607 return CONFIG_SYS_MMC_ENV_DEV;
613 #ifdef CONFIG_SPL_BUILD
615 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
617 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
619 if (spl == INVALID_SPL_HEADER)
622 /* Promote the header version for U-Boot proper, if needed. */
623 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
624 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
626 spl->dram_size = dram_size >> 20;
629 void sunxi_board_init(void)
631 int power_failed = 0;
633 #ifdef CONFIG_LED_STATUS
634 if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
638 #ifdef CONFIG_SY8106A_POWER
639 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
642 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
643 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
644 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
645 power_failed = axp_init();
647 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
648 defined CONFIG_AXP818_POWER
649 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
651 #if !defined(CONFIG_AXP305_POWER)
652 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
653 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
655 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
656 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
658 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
659 defined CONFIG_AXP818_POWER
660 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
663 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
664 defined CONFIG_AXP818_POWER
665 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
667 #if !defined(CONFIG_AXP305_POWER)
668 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
670 #if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
671 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
673 #ifdef CONFIG_AXP209_POWER
674 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
677 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
678 defined(CONFIG_AXP818_POWER)
679 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
680 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
681 #if !defined CONFIG_AXP809_POWER
682 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
683 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
685 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
686 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
687 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
690 #ifdef CONFIG_AXP818_POWER
691 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
692 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
693 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
696 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
697 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
701 gd->ram_size = sunxi_dram_init();
702 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
706 sunxi_spl_store_dram_size(gd->ram_size);
709 * Only clock up the CPU to full speed if we are reasonably
710 * assured it's being powered with suitable core voltage
713 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
715 printf("Failed to set core voltage! Can't set CPU frequency\n");
719 #ifdef CONFIG_USB_GADGET
720 int g_dnl_board_usb_cable_connected(void)
726 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
728 pr_err("%s: Cannot find USB device\n", __func__);
732 ret = generic_phy_get_by_name(dev, "usb", &phy);
734 pr_err("failed to get %s USB PHY\n", dev->name);
738 ret = generic_phy_init(&phy);
740 pr_debug("failed to init %s USB PHY\n", dev->name);
744 ret = sun4i_usb_phy_vbus_detect(&phy);
746 pr_err("A charger is plugged into the OTG\n");
754 #ifdef CONFIG_SERIAL_TAG
755 void get_board_serial(struct tag_serialnr *serialnr)
758 unsigned long long serial;
760 serial_string = env_get("serial#");
763 serial = simple_strtoull(serial_string, NULL, 16);
765 serialnr->high = (unsigned int) (serial >> 32);
766 serialnr->low = (unsigned int) (serial & 0xffffffff);
775 * Check the SPL header for the "sunxi" variant. If found: parse values
776 * that might have been passed by the loader ("fel" utility), and update
777 * the environment accordingly.
779 static void parse_spl_header(const uint32_t spl_addr)
781 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
783 if (spl == INVALID_SPL_HEADER)
786 if (!spl->fel_script_address)
789 if (spl->fel_uEnv_length != 0) {
791 * data is expected in uEnv.txt compatible format, so "env
792 * import -t" the string(s) at fel_script_address right away.
794 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
795 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
798 /* otherwise assume .scr format (mkimage-type script) */
799 env_set_hex("fel_scriptaddr", spl->fel_script_address);
802 static bool get_unique_sid(unsigned int *sid)
804 if (sunxi_get_sid(sid) != 0)
811 * The single words 1 - 3 of the SID have quite a few bits
812 * which are the same on many models, so we take a crc32
813 * of all 3 words, to get a more unique value.
815 * Note we only do this on newer SoCs as we cannot change
816 * the algorithm on older SoCs since those have been using
817 * fixed mac-addresses based on only using word 3 for a
818 * long time and changing a fixed mac-address with an
819 * u-boot update is not good.
821 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
822 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
823 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
824 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
827 /* Ensure the NIC specific bytes of the mac are not all 0 */
828 if ((sid[3] & 0xffffff) == 0)
835 * Note this function gets called multiple times.
836 * It must not make any changes to env variables which already exist.
838 static void setup_environment(const void *fdt)
840 char serial_string[17] = { 0 };
846 if (!get_unique_sid(sid))
849 for (i = 0; i < 4; i++) {
850 sprintf(ethaddr, "ethernet%d", i);
851 if (!fdt_get_alias(fdt, ethaddr))
855 strcpy(ethaddr, "ethaddr");
857 sprintf(ethaddr, "eth%daddr", i);
859 if (env_get(ethaddr))
862 /* Non OUI / registered MAC address */
863 mac_addr[0] = (i << 4) | 0x02;
864 mac_addr[1] = (sid[0] >> 0) & 0xff;
865 mac_addr[2] = (sid[3] >> 24) & 0xff;
866 mac_addr[3] = (sid[3] >> 16) & 0xff;
867 mac_addr[4] = (sid[3] >> 8) & 0xff;
868 mac_addr[5] = (sid[3] >> 0) & 0xff;
870 eth_env_set_enetaddr(ethaddr, mac_addr);
873 if (!env_get("serial#")) {
874 snprintf(serial_string, sizeof(serial_string),
875 "%08x%08x", sid[0], sid[3]);
877 env_set("serial#", serial_string);
881 int misc_init_r(void)
883 const char *spl_dt_name;
886 env_set("fel_booted", NULL);
887 env_set("fel_scriptaddr", NULL);
888 env_set("mmc_bootdev", NULL);
890 boot = sunxi_get_boot_device();
891 /* determine if we are running in FEL mode */
892 if (boot == BOOT_DEVICE_BOARD) {
893 env_set("fel_booted", "1");
894 parse_spl_header(SPL_ADDR);
895 /* or if we booted from MMC, and which one */
896 } else if (boot == BOOT_DEVICE_MMC1) {
897 env_set("mmc_bootdev", "0");
898 } else if (boot == BOOT_DEVICE_MMC2) {
899 env_set("mmc_bootdev", "1");
902 /* Set fdtfile to match the FIT configuration chosen in SPL. */
903 spl_dt_name = get_spl_dt_name();
905 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
908 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
909 env_set("fdtfile", str);
912 setup_environment(gd->fdt_blob);
917 int board_late_init(void)
919 #ifdef CONFIG_USB_ETHER
926 static void bluetooth_dt_fixup(void *blob)
928 /* Some devices ship with a Bluetooth controller default address.
929 * Set a valid address through the device tree.
931 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
935 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
938 if (eth_env_get_enetaddr("bdaddr", tmp)) {
939 /* Convert between the binary formats of the corresponding stacks */
940 for (i = 0; i < ETH_ALEN; ++i)
941 bdaddr[i] = tmp[ETH_ALEN - i - 1];
943 if (!get_unique_sid(sid))
946 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
947 bdaddr[1] = (sid[3] >> 8) & 0xff;
948 bdaddr[2] = (sid[3] >> 16) & 0xff;
949 bdaddr[3] = (sid[3] >> 24) & 0xff;
950 bdaddr[4] = (sid[0] >> 0) & 0xff;
954 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
955 "local-bd-address", bdaddr, ETH_ALEN, 1);
958 int ft_board_setup(void *blob, struct bd_info *bd)
960 int __maybe_unused r;
963 * Call setup_environment again in case the boot fdt has
964 * ethernet aliases the u-boot copy does not have.
966 setup_environment(blob);
968 bluetooth_dt_fixup(blob);
970 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
971 r = sunxi_simplefb_setup(blob);
978 #ifdef CONFIG_SPL_LOAD_FIT
980 static void set_spl_dt_name(const char *name)
982 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
984 if (spl == INVALID_SPL_HEADER)
987 /* Promote the header version for U-Boot proper, if needed. */
988 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
989 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
991 strcpy((char *)&spl->string_pool, name);
992 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
995 int board_fit_config_name_match(const char *name)
997 const char *best_dt_name = get_spl_dt_name();
1000 #ifdef CONFIG_DEFAULT_DEVICE_TREE
1001 if (best_dt_name == NULL)
1002 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
1005 if (best_dt_name == NULL) {
1006 /* No DT name was provided, so accept the first config. */
1009 #ifdef CONFIG_PINE64_DT_SELECTION
1010 if (strstr(best_dt_name, "-pine64-plus")) {
1011 /* Differentiate the Pine A64 boards by their DRAM size. */
1012 if ((gd->ram_size == 512 * 1024 * 1024))
1013 best_dt_name = "sun50i-a64-pine64";
1016 #ifdef CONFIG_PINEPHONE_DT_SELECTION
1017 if (strstr(best_dt_name, "-pinephone")) {
1018 /* Differentiate the PinePhone revisions by GPIO inputs. */
1019 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
1020 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
1021 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
1024 /* PL6 is pulled low by the modem on v1.2. */
1025 if (gpio_get_value(SUNXI_GPL(6)) == 0)
1026 best_dt_name = "sun50i-a64-pinephone-1.2";
1028 best_dt_name = "sun50i-a64-pinephone-1.1";
1030 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
1031 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
1032 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
1036 ret = strcmp(name, best_dt_name);
1039 * If one of the FIT configurations matches the most accurate DT name,
1040 * update the SPL header to provide that DT name to U-Boot proper.
1043 set_spl_dt_name(best_dt_name);