1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
22 #include <generic-phy.h>
23 #include <phy-sun4i-usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/display.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/spl.h>
32 #include <linux/delay.h>
33 #include <u-boot/crc.h>
35 #include <asm/armv7.h>
39 #include <u-boot/crc.h>
40 #include <env_internal.h>
41 #include <linux/libfdt.h>
46 #include <asm/setup.h>
48 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
49 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
50 int soft_i2c_gpio_sda;
51 int soft_i2c_gpio_scl;
53 static int soft_i2c_board_init(void)
57 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
58 if (soft_i2c_gpio_sda < 0) {
59 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
60 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
61 return soft_i2c_gpio_sda;
63 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
65 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
66 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
70 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
71 if (soft_i2c_gpio_scl < 0) {
72 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
73 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
74 return soft_i2c_gpio_scl;
76 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
78 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
79 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
86 static int soft_i2c_board_init(void) { return 0; }
89 DECLARE_GLOBAL_DATA_PTR;
91 void i2c_init_board(void)
93 #ifdef CONFIG_I2C0_ENABLE
94 #if defined(CONFIG_MACH_SUN4I) || \
95 defined(CONFIG_MACH_SUN5I) || \
96 defined(CONFIG_MACH_SUN7I) || \
97 defined(CONFIG_MACH_SUN8I_R40)
98 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
100 clock_twi_onoff(0, 1);
101 #elif defined(CONFIG_MACH_SUN6I)
102 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
104 clock_twi_onoff(0, 1);
105 #elif defined(CONFIG_MACH_SUN8I)
106 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
107 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
108 clock_twi_onoff(0, 1);
109 #elif defined(CONFIG_MACH_SUN50I)
110 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
111 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
112 clock_twi_onoff(0, 1);
116 #ifdef CONFIG_I2C1_ENABLE
117 #if defined(CONFIG_MACH_SUN4I) || \
118 defined(CONFIG_MACH_SUN7I) || \
119 defined(CONFIG_MACH_SUN8I_R40)
120 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
122 clock_twi_onoff(1, 1);
123 #elif defined(CONFIG_MACH_SUN5I)
124 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
125 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
126 clock_twi_onoff(1, 1);
127 #elif defined(CONFIG_MACH_SUN6I)
128 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
129 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
130 clock_twi_onoff(1, 1);
131 #elif defined(CONFIG_MACH_SUN8I)
132 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
134 clock_twi_onoff(1, 1);
135 #elif defined(CONFIG_MACH_SUN50I)
136 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
137 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
138 clock_twi_onoff(1, 1);
142 #ifdef CONFIG_I2C2_ENABLE
143 #if defined(CONFIG_MACH_SUN4I) || \
144 defined(CONFIG_MACH_SUN7I) || \
145 defined(CONFIG_MACH_SUN8I_R40)
146 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
147 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
148 clock_twi_onoff(2, 1);
149 #elif defined(CONFIG_MACH_SUN5I)
150 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
151 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
152 clock_twi_onoff(2, 1);
153 #elif defined(CONFIG_MACH_SUN6I)
154 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
155 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
156 clock_twi_onoff(2, 1);
157 #elif defined(CONFIG_MACH_SUN8I)
158 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
159 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
160 clock_twi_onoff(2, 1);
161 #elif defined(CONFIG_MACH_SUN50I)
162 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
163 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
164 clock_twi_onoff(2, 1);
168 #ifdef CONFIG_I2C3_ENABLE
169 #if defined(CONFIG_MACH_SUN6I)
170 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
171 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
172 clock_twi_onoff(3, 1);
173 #elif defined(CONFIG_MACH_SUN7I) || \
174 defined(CONFIG_MACH_SUN8I_R40)
175 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
176 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
177 clock_twi_onoff(3, 1);
181 #ifdef CONFIG_I2C4_ENABLE
182 #if defined(CONFIG_MACH_SUN7I) || \
183 defined(CONFIG_MACH_SUN8I_R40)
184 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
185 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
186 clock_twi_onoff(4, 1);
190 #ifdef CONFIG_R_I2C_ENABLE
191 #ifdef CONFIG_MACH_SUN50I
192 clock_twi_onoff(5, 1);
193 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
194 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
196 clock_twi_onoff(5, 1);
197 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
198 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
203 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
204 enum env_location env_get_location(enum env_operation op, int prio)
220 static void mmc_pinmux_setup(int sdc);
223 /* add board specific code here */
226 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
228 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
231 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
232 debug("id_pfr1: 0x%08x\n", id_pfr1);
233 /* Generic Timer Extension available? */
234 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
237 debug("Setting CNTFRQ\n");
240 * CNTFRQ is a secure register, so we will crash if we try to
241 * write this from the non-secure world (read is OK, though).
242 * In case some bootcode has already set the correct value,
243 * we avoid the risk of writing to it.
245 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
246 if (freq != COUNTER_FREQUENCY) {
247 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
248 freq, COUNTER_FREQUENCY);
249 #ifdef CONFIG_NON_SECURE
250 printf("arch timer frequency is wrong, but cannot adjust it\n");
252 asm volatile("mcr p15, 0, %0, c14, c0, 0"
253 : : "r"(COUNTER_FREQUENCY));
257 #endif /* !CONFIG_ARM64 */
259 ret = axp_gpio_init();
263 #ifdef CONFIG_SATAPWR
264 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
265 gpio_request(satapwr_pin, "satapwr");
266 gpio_direction_output(satapwr_pin, 1);
267 /* Give attached sata device time to power-up to avoid link timeouts */
271 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
272 gpio_request(macpwr_pin, "macpwr");
273 gpio_direction_output(macpwr_pin, 1);
278 * Temporary workaround for enabling I2C clocks until proper sunxi DM
279 * clk, reset and pinctrl drivers land.
286 * Temporary workaround for enabling MMC clocks until a sunxi DM
287 * pinctrl driver lands.
289 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
290 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
291 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
293 #endif /* CONFIG_DM_MMC */
295 /* Uses dm gpio code so do this here and not in i2c_init_board() */
296 return soft_i2c_board_init();
300 * On older SoCs the SPL is actually at address zero, so using NULL as
301 * an error value does not work.
303 #define INVALID_SPL_HEADER ((void *)~0UL)
305 static struct boot_file_head * get_spl_header(uint8_t req_version)
307 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
308 uint8_t spl_header_version = spl->spl_signature[3];
310 /* Is there really the SPL header (still) there? */
311 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
312 return INVALID_SPL_HEADER;
314 if (spl_header_version < req_version) {
315 printf("sunxi SPL version mismatch: expected %u, got %u\n",
316 req_version, spl_header_version);
317 return INVALID_SPL_HEADER;
323 #ifdef CONFIG_SPL_LOAD_FIT
324 static const char *get_spl_dt_name(void)
326 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
328 /* Check if there is a DT name stored in the SPL header. */
329 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
330 return (char *)spl + spl->dt_name_offset;
338 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
340 if (spl == INVALID_SPL_HEADER)
341 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
344 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
346 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
347 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
352 #if defined(CONFIG_NAND_SUNXI)
353 static void nand_pinmux_setup(void)
357 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
358 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
360 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
361 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
362 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
364 /* sun4i / sun7i do have a PC23, but it is not used for nand,
365 * only sun7i has a PC24 */
366 #ifdef CONFIG_MACH_SUN7I
367 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
371 static void nand_clock_setup(void)
373 struct sunxi_ccm_reg *const ccm =
374 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
376 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
377 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
378 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
379 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
381 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
384 void board_nand_init(void)
388 #ifndef CONFIG_SPL_BUILD
395 static void mmc_pinmux_setup(int sdc)
398 __maybe_unused int pins;
403 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
404 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
405 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
406 sunxi_gpio_set_drv(pin, 2);
411 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
413 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
414 defined(CONFIG_MACH_SUN8I_R40)
415 if (pins == SUNXI_GPIO_H) {
416 /* SDC1: PH22-PH-27 */
417 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
418 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
419 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
420 sunxi_gpio_set_drv(pin, 2);
424 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
425 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
426 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
427 sunxi_gpio_set_drv(pin, 2);
430 #elif defined(CONFIG_MACH_SUN5I)
432 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
433 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
434 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
435 sunxi_gpio_set_drv(pin, 2);
437 #elif defined(CONFIG_MACH_SUN6I)
439 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
440 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
441 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
442 sunxi_gpio_set_drv(pin, 2);
444 #elif defined(CONFIG_MACH_SUN8I)
445 if (pins == SUNXI_GPIO_D) {
447 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
448 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
449 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
450 sunxi_gpio_set_drv(pin, 2);
454 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
455 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
456 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
457 sunxi_gpio_set_drv(pin, 2);
464 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
466 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
468 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
469 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
470 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
471 sunxi_gpio_set_drv(pin, 2);
473 #elif defined(CONFIG_MACH_SUN5I)
474 if (pins == SUNXI_GPIO_E) {
476 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
477 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
478 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
479 sunxi_gpio_set_drv(pin, 2);
483 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
484 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
485 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
486 sunxi_gpio_set_drv(pin, 2);
489 #elif defined(CONFIG_MACH_SUN6I)
490 if (pins == SUNXI_GPIO_A) {
492 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
493 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
494 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
495 sunxi_gpio_set_drv(pin, 2);
498 /* SDC2: PC6-PC15, PC24 */
499 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
500 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
501 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
502 sunxi_gpio_set_drv(pin, 2);
505 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
506 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
507 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
509 #elif defined(CONFIG_MACH_SUN8I_R40)
510 /* SDC2: PC6-PC15, PC24 */
511 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
512 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
513 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
514 sunxi_gpio_set_drv(pin, 2);
517 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
518 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
519 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
520 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
521 /* SDC2: PC5-PC6, PC8-PC16 */
522 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
523 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
524 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
525 sunxi_gpio_set_drv(pin, 2);
528 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
529 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
530 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
531 sunxi_gpio_set_drv(pin, 2);
533 #elif defined(CONFIG_MACH_SUN50I_H6)
535 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
536 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
537 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
538 sunxi_gpio_set_drv(pin, 2);
540 #elif defined(CONFIG_MACH_SUN9I)
542 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
543 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
544 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
545 sunxi_gpio_set_drv(pin, 2);
551 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
553 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
554 defined(CONFIG_MACH_SUN8I_R40)
556 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
557 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
558 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
559 sunxi_gpio_set_drv(pin, 2);
561 #elif defined(CONFIG_MACH_SUN6I)
562 if (pins == SUNXI_GPIO_A) {
564 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
565 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
566 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
567 sunxi_gpio_set_drv(pin, 2);
570 /* SDC3: PC6-PC15, PC24 */
571 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
572 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
573 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
574 sunxi_gpio_set_drv(pin, 2);
577 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
578 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
579 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
585 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
590 int board_mmc_init(struct bd_info *bis)
592 __maybe_unused struct mmc *mmc0, *mmc1;
594 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
595 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
599 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
600 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
601 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
610 #ifdef CONFIG_SPL_BUILD
612 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
614 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
616 if (spl == INVALID_SPL_HEADER)
619 /* Promote the header version for U-Boot proper, if needed. */
620 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
621 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
623 spl->dram_size = dram_size >> 20;
626 void sunxi_board_init(void)
628 int power_failed = 0;
630 #ifdef CONFIG_SY8106A_POWER
631 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
634 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
635 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
636 defined CONFIG_AXP818_POWER
637 power_failed = axp_init();
639 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
640 defined CONFIG_AXP818_POWER
641 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
643 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
644 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
645 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
646 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
648 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
649 defined CONFIG_AXP818_POWER
650 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
653 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
654 defined CONFIG_AXP818_POWER
655 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
657 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
658 #if !defined(CONFIG_AXP152_POWER)
659 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
661 #ifdef CONFIG_AXP209_POWER
662 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
665 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
666 defined(CONFIG_AXP818_POWER)
667 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
668 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
669 #if !defined CONFIG_AXP809_POWER
670 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
671 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
673 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
674 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
675 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
678 #ifdef CONFIG_AXP818_POWER
679 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
680 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
681 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
684 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
685 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
689 gd->ram_size = sunxi_dram_init();
690 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
694 sunxi_spl_store_dram_size(gd->ram_size);
697 * Only clock up the CPU to full speed if we are reasonably
698 * assured it's being powered with suitable core voltage
701 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
703 printf("Failed to set core voltage! Can't set CPU frequency\n");
707 #ifdef CONFIG_USB_GADGET
708 int g_dnl_board_usb_cable_connected(void)
714 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
716 pr_err("%s: Cannot find USB device\n", __func__);
720 ret = generic_phy_get_by_name(dev, "usb", &phy);
722 pr_err("failed to get %s USB PHY\n", dev->name);
726 ret = generic_phy_init(&phy);
728 pr_debug("failed to init %s USB PHY\n", dev->name);
732 ret = sun4i_usb_phy_vbus_detect(&phy);
734 pr_err("A charger is plugged into the OTG\n");
742 #ifdef CONFIG_SERIAL_TAG
743 void get_board_serial(struct tag_serialnr *serialnr)
746 unsigned long long serial;
748 serial_string = env_get("serial#");
751 serial = simple_strtoull(serial_string, NULL, 16);
753 serialnr->high = (unsigned int) (serial >> 32);
754 serialnr->low = (unsigned int) (serial & 0xffffffff);
763 * Check the SPL header for the "sunxi" variant. If found: parse values
764 * that might have been passed by the loader ("fel" utility), and update
765 * the environment accordingly.
767 static void parse_spl_header(const uint32_t spl_addr)
769 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
771 if (spl == INVALID_SPL_HEADER)
774 if (!spl->fel_script_address)
777 if (spl->fel_uEnv_length != 0) {
779 * data is expected in uEnv.txt compatible format, so "env
780 * import -t" the string(s) at fel_script_address right away.
782 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
783 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
786 /* otherwise assume .scr format (mkimage-type script) */
787 env_set_hex("fel_scriptaddr", spl->fel_script_address);
791 * Note this function gets called multiple times.
792 * It must not make any changes to env variables which already exist.
794 static void setup_environment(const void *fdt)
796 char serial_string[17] = { 0 };
802 ret = sunxi_get_sid(sid);
803 if (ret == 0 && sid[0] != 0) {
805 * The single words 1 - 3 of the SID have quite a few bits
806 * which are the same on many models, so we take a crc32
807 * of all 3 words, to get a more unique value.
809 * Note we only do this on newer SoCs as we cannot change
810 * the algorithm on older SoCs since those have been using
811 * fixed mac-addresses based on only using word 3 for a
812 * long time and changing a fixed mac-address with an
813 * u-boot update is not good.
815 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
816 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
817 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
818 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
821 /* Ensure the NIC specific bytes of the mac are not all 0 */
822 if ((sid[3] & 0xffffff) == 0)
825 for (i = 0; i < 4; i++) {
826 sprintf(ethaddr, "ethernet%d", i);
827 if (!fdt_get_alias(fdt, ethaddr))
831 strcpy(ethaddr, "ethaddr");
833 sprintf(ethaddr, "eth%daddr", i);
835 if (env_get(ethaddr))
838 /* Non OUI / registered MAC address */
839 mac_addr[0] = (i << 4) | 0x02;
840 mac_addr[1] = (sid[0] >> 0) & 0xff;
841 mac_addr[2] = (sid[3] >> 24) & 0xff;
842 mac_addr[3] = (sid[3] >> 16) & 0xff;
843 mac_addr[4] = (sid[3] >> 8) & 0xff;
844 mac_addr[5] = (sid[3] >> 0) & 0xff;
846 eth_env_set_enetaddr(ethaddr, mac_addr);
849 if (!env_get("serial#")) {
850 snprintf(serial_string, sizeof(serial_string),
851 "%08x%08x", sid[0], sid[3]);
853 env_set("serial#", serial_string);
858 int misc_init_r(void)
862 env_set("fel_booted", NULL);
863 env_set("fel_scriptaddr", NULL);
864 env_set("mmc_bootdev", NULL);
866 boot = sunxi_get_boot_device();
867 /* determine if we are running in FEL mode */
868 if (boot == BOOT_DEVICE_BOARD) {
869 env_set("fel_booted", "1");
870 parse_spl_header(SPL_ADDR);
871 /* or if we booted from MMC, and which one */
872 } else if (boot == BOOT_DEVICE_MMC1) {
873 env_set("mmc_bootdev", "0");
874 } else if (boot == BOOT_DEVICE_MMC2) {
875 env_set("mmc_bootdev", "1");
878 setup_environment(gd->fdt_blob);
880 #ifdef CONFIG_USB_ETHER
887 int ft_board_setup(void *blob, struct bd_info *bd)
889 int __maybe_unused r;
892 * Call setup_environment again in case the boot fdt has
893 * ethernet aliases the u-boot copy does not have.
895 setup_environment(blob);
897 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
898 r = sunxi_simplefb_setup(blob);
905 #ifdef CONFIG_SPL_LOAD_FIT
906 int board_fit_config_name_match(const char *name)
908 const char *best_dt_name = get_spl_dt_name();
910 #ifdef CONFIG_DEFAULT_DEVICE_TREE
911 if (best_dt_name == NULL)
912 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
915 if (best_dt_name == NULL) {
916 /* No DT name was provided, so accept the first config. */
919 #ifdef CONFIG_PINE64_DT_SELECTION
920 if (strstr(best_dt_name, "-pine64-plus")) {
921 /* Differentiate the Pine A64 boards by their DRAM size. */
922 if ((gd->ram_size == 512 * 1024 * 1024))
923 best_dt_name = "sun50i-a64-pine64";
926 #ifdef CONFIG_PINEPHONE_DT_SELECTION
927 if (strstr(best_dt_name, "-pinephone")) {
928 /* Differentiate the PinePhone revisions by GPIO inputs. */
929 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
930 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
931 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
934 /* PL6 is pulled low by the modem on v1.2. */
935 if (gpio_get_value(SUNXI_GPL(6)) == 0)
936 best_dt_name = "sun50i-a64-pinephone-1.2";
938 best_dt_name = "sun50i-a64-pinephone-1.1";
940 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
941 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
942 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
946 return strcmp(name, best_dt_name);