1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
21 #include <generic-phy.h>
22 #include <phy-sun4i-usb.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/cpu.h>
25 #include <asm/arch/display.h>
26 #include <asm/arch/dram.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc.h>
29 #include <asm/arch/spl.h>
30 #include <u-boot/crc.h>
32 #include <asm/armv7.h>
36 #include <u-boot/crc.h>
37 #include <env_internal.h>
38 #include <linux/libfdt.h>
43 #include <asm/setup.h>
45 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
46 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
47 int soft_i2c_gpio_sda;
48 int soft_i2c_gpio_scl;
50 static int soft_i2c_board_init(void)
54 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
55 if (soft_i2c_gpio_sda < 0) {
56 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
57 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
58 return soft_i2c_gpio_sda;
60 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
62 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
63 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
67 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
68 if (soft_i2c_gpio_scl < 0) {
69 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
70 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
71 return soft_i2c_gpio_scl;
73 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
75 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
76 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
83 static int soft_i2c_board_init(void) { return 0; }
86 DECLARE_GLOBAL_DATA_PTR;
88 void i2c_init_board(void)
90 #ifdef CONFIG_I2C0_ENABLE
91 #if defined(CONFIG_MACH_SUN4I) || \
92 defined(CONFIG_MACH_SUN5I) || \
93 defined(CONFIG_MACH_SUN7I) || \
94 defined(CONFIG_MACH_SUN8I_R40)
95 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
96 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
97 clock_twi_onoff(0, 1);
98 #elif defined(CONFIG_MACH_SUN6I)
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
101 clock_twi_onoff(0, 1);
102 #elif defined(CONFIG_MACH_SUN8I)
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
105 clock_twi_onoff(0, 1);
106 #elif defined(CONFIG_MACH_SUN50I)
107 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
108 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
109 clock_twi_onoff(0, 1);
113 #ifdef CONFIG_I2C1_ENABLE
114 #if defined(CONFIG_MACH_SUN4I) || \
115 defined(CONFIG_MACH_SUN7I) || \
116 defined(CONFIG_MACH_SUN8I_R40)
117 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
118 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
119 clock_twi_onoff(1, 1);
120 #elif defined(CONFIG_MACH_SUN5I)
121 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
122 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
123 clock_twi_onoff(1, 1);
124 #elif defined(CONFIG_MACH_SUN6I)
125 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
126 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
127 clock_twi_onoff(1, 1);
128 #elif defined(CONFIG_MACH_SUN8I)
129 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
130 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
131 clock_twi_onoff(1, 1);
132 #elif defined(CONFIG_MACH_SUN50I)
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
134 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
135 clock_twi_onoff(1, 1);
139 #ifdef CONFIG_I2C2_ENABLE
140 #if defined(CONFIG_MACH_SUN4I) || \
141 defined(CONFIG_MACH_SUN7I) || \
142 defined(CONFIG_MACH_SUN8I_R40)
143 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
144 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
145 clock_twi_onoff(2, 1);
146 #elif defined(CONFIG_MACH_SUN5I)
147 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
148 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
149 clock_twi_onoff(2, 1);
150 #elif defined(CONFIG_MACH_SUN6I)
151 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
152 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
153 clock_twi_onoff(2, 1);
154 #elif defined(CONFIG_MACH_SUN8I)
155 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
156 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
157 clock_twi_onoff(2, 1);
158 #elif defined(CONFIG_MACH_SUN50I)
159 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
160 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
161 clock_twi_onoff(2, 1);
165 #ifdef CONFIG_I2C3_ENABLE
166 #if defined(CONFIG_MACH_SUN6I)
167 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
168 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
169 clock_twi_onoff(3, 1);
170 #elif defined(CONFIG_MACH_SUN7I) || \
171 defined(CONFIG_MACH_SUN8I_R40)
172 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
173 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
174 clock_twi_onoff(3, 1);
178 #ifdef CONFIG_I2C4_ENABLE
179 #if defined(CONFIG_MACH_SUN7I) || \
180 defined(CONFIG_MACH_SUN8I_R40)
181 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
182 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
183 clock_twi_onoff(4, 1);
187 #ifdef CONFIG_R_I2C_ENABLE
188 #ifdef CONFIG_MACH_SUN50I
189 clock_twi_onoff(5, 1);
190 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
191 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
193 clock_twi_onoff(5, 1);
194 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
195 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
200 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
201 enum env_location env_get_location(enum env_operation op, int prio)
217 static void mmc_pinmux_setup(int sdc);
220 /* add board specific code here */
223 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
225 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
228 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
229 debug("id_pfr1: 0x%08x\n", id_pfr1);
230 /* Generic Timer Extension available? */
231 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
234 debug("Setting CNTFRQ\n");
237 * CNTFRQ is a secure register, so we will crash if we try to
238 * write this from the non-secure world (read is OK, though).
239 * In case some bootcode has already set the correct value,
240 * we avoid the risk of writing to it.
242 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
243 if (freq != COUNTER_FREQUENCY) {
244 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
245 freq, COUNTER_FREQUENCY);
246 #ifdef CONFIG_NON_SECURE
247 printf("arch timer frequency is wrong, but cannot adjust it\n");
249 asm volatile("mcr p15, 0, %0, c14, c0, 0"
250 : : "r"(COUNTER_FREQUENCY));
254 #endif /* !CONFIG_ARM64 */
256 ret = axp_gpio_init();
260 #ifdef CONFIG_SATAPWR
261 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
262 gpio_request(satapwr_pin, "satapwr");
263 gpio_direction_output(satapwr_pin, 1);
264 /* Give attached sata device time to power-up to avoid link timeouts */
268 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
269 gpio_request(macpwr_pin, "macpwr");
270 gpio_direction_output(macpwr_pin, 1);
275 * Temporary workaround for enabling I2C clocks until proper sunxi DM
276 * clk, reset and pinctrl drivers land.
283 * Temporary workaround for enabling MMC clocks until a sunxi DM
284 * pinctrl driver lands.
286 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
287 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
288 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
290 #endif /* CONFIG_DM_MMC */
292 /* Uses dm gpio code so do this here and not in i2c_init_board() */
293 return soft_i2c_board_init();
297 * On older SoCs the SPL is actually at address zero, so using NULL as
298 * an error value does not work.
300 #define INVALID_SPL_HEADER ((void *)~0UL)
302 static struct boot_file_head * get_spl_header(uint8_t req_version)
304 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
305 uint8_t spl_header_version = spl->spl_signature[3];
307 /* Is there really the SPL header (still) there? */
308 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
309 return INVALID_SPL_HEADER;
311 if (spl_header_version < req_version) {
312 printf("sunxi SPL version mismatch: expected %u, got %u\n",
313 req_version, spl_header_version);
314 return INVALID_SPL_HEADER;
322 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
324 if (spl == INVALID_SPL_HEADER)
325 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
328 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
330 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
331 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
336 #if defined(CONFIG_NAND_SUNXI)
337 static void nand_pinmux_setup(void)
341 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
342 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
344 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
345 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
346 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
348 /* sun4i / sun7i do have a PC23, but it is not used for nand,
349 * only sun7i has a PC24 */
350 #ifdef CONFIG_MACH_SUN7I
351 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
355 static void nand_clock_setup(void)
357 struct sunxi_ccm_reg *const ccm =
358 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
360 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
361 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
362 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
363 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
365 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
368 void board_nand_init(void)
372 #ifndef CONFIG_SPL_BUILD
379 static void mmc_pinmux_setup(int sdc)
382 __maybe_unused int pins;
387 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
388 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
389 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
390 sunxi_gpio_set_drv(pin, 2);
395 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
397 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
398 defined(CONFIG_MACH_SUN8I_R40)
399 if (pins == SUNXI_GPIO_H) {
400 /* SDC1: PH22-PH-27 */
401 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
402 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
403 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
404 sunxi_gpio_set_drv(pin, 2);
408 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
409 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
410 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
411 sunxi_gpio_set_drv(pin, 2);
414 #elif defined(CONFIG_MACH_SUN5I)
416 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
417 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
418 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
419 sunxi_gpio_set_drv(pin, 2);
421 #elif defined(CONFIG_MACH_SUN6I)
423 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
424 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
425 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
426 sunxi_gpio_set_drv(pin, 2);
428 #elif defined(CONFIG_MACH_SUN8I)
429 if (pins == SUNXI_GPIO_D) {
431 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
432 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
433 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
434 sunxi_gpio_set_drv(pin, 2);
438 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
439 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
440 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
441 sunxi_gpio_set_drv(pin, 2);
448 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
450 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
452 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
453 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
454 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
455 sunxi_gpio_set_drv(pin, 2);
457 #elif defined(CONFIG_MACH_SUN5I)
458 if (pins == SUNXI_GPIO_E) {
460 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
461 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
462 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
463 sunxi_gpio_set_drv(pin, 2);
467 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
468 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
469 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
470 sunxi_gpio_set_drv(pin, 2);
473 #elif defined(CONFIG_MACH_SUN6I)
474 if (pins == SUNXI_GPIO_A) {
476 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
477 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
478 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
479 sunxi_gpio_set_drv(pin, 2);
482 /* SDC2: PC6-PC15, PC24 */
483 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
484 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
485 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
486 sunxi_gpio_set_drv(pin, 2);
489 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
490 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
491 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
493 #elif defined(CONFIG_MACH_SUN8I_R40)
494 /* SDC2: PC6-PC15, PC24 */
495 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
496 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
497 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
498 sunxi_gpio_set_drv(pin, 2);
501 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
502 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
503 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
504 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
505 /* SDC2: PC5-PC6, PC8-PC16 */
506 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
507 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
508 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
509 sunxi_gpio_set_drv(pin, 2);
512 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
513 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
514 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
515 sunxi_gpio_set_drv(pin, 2);
517 #elif defined(CONFIG_MACH_SUN50I_H6)
519 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
520 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
521 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
522 sunxi_gpio_set_drv(pin, 2);
524 #elif defined(CONFIG_MACH_SUN9I)
526 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
527 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
528 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
529 sunxi_gpio_set_drv(pin, 2);
535 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
537 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
538 defined(CONFIG_MACH_SUN8I_R40)
540 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
541 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
542 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
543 sunxi_gpio_set_drv(pin, 2);
545 #elif defined(CONFIG_MACH_SUN6I)
546 if (pins == SUNXI_GPIO_A) {
548 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
549 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
550 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
551 sunxi_gpio_set_drv(pin, 2);
554 /* SDC3: PC6-PC15, PC24 */
555 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
556 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
557 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
558 sunxi_gpio_set_drv(pin, 2);
561 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
562 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
563 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
569 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
574 int board_mmc_init(bd_t *bis)
576 __maybe_unused struct mmc *mmc0, *mmc1;
578 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
579 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
583 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
584 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
585 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
594 #ifdef CONFIG_SPL_BUILD
596 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
598 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
600 if (spl == INVALID_SPL_HEADER)
603 /* Promote the header version for U-Boot proper, if needed. */
604 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
605 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
607 spl->dram_size = dram_size >> 20;
610 void sunxi_board_init(void)
612 int power_failed = 0;
614 #ifdef CONFIG_SY8106A_POWER
615 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
618 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
619 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
620 defined CONFIG_AXP818_POWER
621 power_failed = axp_init();
623 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
624 defined CONFIG_AXP818_POWER
625 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
627 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
628 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
629 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
630 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
632 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
633 defined CONFIG_AXP818_POWER
634 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
637 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
638 defined CONFIG_AXP818_POWER
639 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
641 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
642 #if !defined(CONFIG_AXP152_POWER)
643 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
645 #ifdef CONFIG_AXP209_POWER
646 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
649 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
650 defined(CONFIG_AXP818_POWER)
651 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
652 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
653 #if !defined CONFIG_AXP809_POWER
654 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
655 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
657 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
658 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
659 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
662 #ifdef CONFIG_AXP818_POWER
663 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
664 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
665 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
668 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
669 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
673 gd->ram_size = sunxi_dram_init();
674 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
678 sunxi_spl_store_dram_size(gd->ram_size);
681 * Only clock up the CPU to full speed if we are reasonably
682 * assured it's being powered with suitable core voltage
685 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
687 printf("Failed to set core voltage! Can't set CPU frequency\n");
691 #ifdef CONFIG_USB_GADGET
692 int g_dnl_board_usb_cable_connected(void)
698 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
700 pr_err("%s: Cannot find USB device\n", __func__);
704 ret = generic_phy_get_by_name(dev, "usb", &phy);
706 pr_err("failed to get %s USB PHY\n", dev->name);
710 ret = generic_phy_init(&phy);
712 pr_err("failed to init %s USB PHY\n", dev->name);
716 ret = sun4i_usb_phy_vbus_detect(&phy);
718 pr_err("A charger is plugged into the OTG\n");
726 #ifdef CONFIG_SERIAL_TAG
727 void get_board_serial(struct tag_serialnr *serialnr)
730 unsigned long long serial;
732 serial_string = env_get("serial#");
735 serial = simple_strtoull(serial_string, NULL, 16);
737 serialnr->high = (unsigned int) (serial >> 32);
738 serialnr->low = (unsigned int) (serial & 0xffffffff);
747 * Check the SPL header for the "sunxi" variant. If found: parse values
748 * that might have been passed by the loader ("fel" utility), and update
749 * the environment accordingly.
751 static void parse_spl_header(const uint32_t spl_addr)
753 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
755 if (spl == INVALID_SPL_HEADER)
758 if (!spl->fel_script_address)
761 if (spl->fel_uEnv_length != 0) {
763 * data is expected in uEnv.txt compatible format, so "env
764 * import -t" the string(s) at fel_script_address right away.
766 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
767 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
770 /* otherwise assume .scr format (mkimage-type script) */
771 env_set_hex("fel_scriptaddr", spl->fel_script_address);
775 * Note this function gets called multiple times.
776 * It must not make any changes to env variables which already exist.
778 static void setup_environment(const void *fdt)
780 char serial_string[17] = { 0 };
786 ret = sunxi_get_sid(sid);
787 if (ret == 0 && sid[0] != 0) {
789 * The single words 1 - 3 of the SID have quite a few bits
790 * which are the same on many models, so we take a crc32
791 * of all 3 words, to get a more unique value.
793 * Note we only do this on newer SoCs as we cannot change
794 * the algorithm on older SoCs since those have been using
795 * fixed mac-addresses based on only using word 3 for a
796 * long time and changing a fixed mac-address with an
797 * u-boot update is not good.
799 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
800 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
801 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
802 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
805 /* Ensure the NIC specific bytes of the mac are not all 0 */
806 if ((sid[3] & 0xffffff) == 0)
809 for (i = 0; i < 4; i++) {
810 sprintf(ethaddr, "ethernet%d", i);
811 if (!fdt_get_alias(fdt, ethaddr))
815 strcpy(ethaddr, "ethaddr");
817 sprintf(ethaddr, "eth%daddr", i);
819 if (env_get(ethaddr))
822 /* Non OUI / registered MAC address */
823 mac_addr[0] = (i << 4) | 0x02;
824 mac_addr[1] = (sid[0] >> 0) & 0xff;
825 mac_addr[2] = (sid[3] >> 24) & 0xff;
826 mac_addr[3] = (sid[3] >> 16) & 0xff;
827 mac_addr[4] = (sid[3] >> 8) & 0xff;
828 mac_addr[5] = (sid[3] >> 0) & 0xff;
830 eth_env_set_enetaddr(ethaddr, mac_addr);
833 if (!env_get("serial#")) {
834 snprintf(serial_string, sizeof(serial_string),
835 "%08x%08x", sid[0], sid[3]);
837 env_set("serial#", serial_string);
842 int misc_init_r(void)
846 env_set("fel_booted", NULL);
847 env_set("fel_scriptaddr", NULL);
848 env_set("mmc_bootdev", NULL);
850 boot = sunxi_get_boot_device();
851 /* determine if we are running in FEL mode */
852 if (boot == BOOT_DEVICE_BOARD) {
853 env_set("fel_booted", "1");
854 parse_spl_header(SPL_ADDR);
855 /* or if we booted from MMC, and which one */
856 } else if (boot == BOOT_DEVICE_MMC1) {
857 env_set("mmc_bootdev", "0");
858 } else if (boot == BOOT_DEVICE_MMC2) {
859 env_set("mmc_bootdev", "1");
862 setup_environment(gd->fdt_blob);
864 #ifdef CONFIG_USB_ETHER
871 int ft_board_setup(void *blob, bd_t *bd)
873 int __maybe_unused r;
876 * Call setup_environment again in case the boot fdt has
877 * ethernet aliases the u-boot copy does not have.
879 setup_environment(blob);
881 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
882 r = sunxi_simplefb_setup(blob);
889 #ifdef CONFIG_SPL_LOAD_FIT
890 int board_fit_config_name_match(const char *name)
892 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
893 const char *cmp_str = (const char *)spl;
895 /* Check if there is a DT name stored in the SPL header and use that. */
896 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
897 cmp_str += spl->dt_name_offset;
899 #ifdef CONFIG_DEFAULT_DEVICE_TREE
900 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
906 #ifdef CONFIG_PINE64_DT_SELECTION
907 /* Differentiate the two Pine64 board DTs by their DRAM size. */
908 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
909 if ((gd->ram_size > 512 * 1024 * 1024))
910 return !strstr(name, "plus");
912 return !!strstr(name, "plus");
914 return strcmp(name, cmp_str);
917 return strcmp(name, cmp_str);