1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
22 #include <generic-phy.h>
23 #include <phy-sun4i-usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/display.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/spl.h>
31 #include <linux/delay.h>
32 #include <u-boot/crc.h>
34 #include <asm/armv7.h>
38 #include <u-boot/crc.h>
39 #include <env_internal.h>
40 #include <linux/libfdt.h>
45 #include <asm/setup.h>
47 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
48 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
49 int soft_i2c_gpio_sda;
50 int soft_i2c_gpio_scl;
52 static int soft_i2c_board_init(void)
56 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
57 if (soft_i2c_gpio_sda < 0) {
58 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
59 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
60 return soft_i2c_gpio_sda;
62 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
64 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
65 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
69 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
70 if (soft_i2c_gpio_scl < 0) {
71 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
72 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
73 return soft_i2c_gpio_scl;
75 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
77 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
78 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
85 static int soft_i2c_board_init(void) { return 0; }
88 DECLARE_GLOBAL_DATA_PTR;
90 void i2c_init_board(void)
92 #ifdef CONFIG_I2C0_ENABLE
93 #if defined(CONFIG_MACH_SUN4I) || \
94 defined(CONFIG_MACH_SUN5I) || \
95 defined(CONFIG_MACH_SUN7I) || \
96 defined(CONFIG_MACH_SUN8I_R40)
97 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
98 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
99 clock_twi_onoff(0, 1);
100 #elif defined(CONFIG_MACH_SUN6I)
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
102 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
103 clock_twi_onoff(0, 1);
104 #elif defined(CONFIG_MACH_SUN8I)
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
106 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
107 clock_twi_onoff(0, 1);
108 #elif defined(CONFIG_MACH_SUN50I)
109 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
110 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
111 clock_twi_onoff(0, 1);
115 #ifdef CONFIG_I2C1_ENABLE
116 #if defined(CONFIG_MACH_SUN4I) || \
117 defined(CONFIG_MACH_SUN7I) || \
118 defined(CONFIG_MACH_SUN8I_R40)
119 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
120 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
121 clock_twi_onoff(1, 1);
122 #elif defined(CONFIG_MACH_SUN5I)
123 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
124 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
125 clock_twi_onoff(1, 1);
126 #elif defined(CONFIG_MACH_SUN6I)
127 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
128 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
129 clock_twi_onoff(1, 1);
130 #elif defined(CONFIG_MACH_SUN8I)
131 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
132 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
133 clock_twi_onoff(1, 1);
134 #elif defined(CONFIG_MACH_SUN50I)
135 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
136 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
137 clock_twi_onoff(1, 1);
141 #ifdef CONFIG_I2C2_ENABLE
142 #if defined(CONFIG_MACH_SUN4I) || \
143 defined(CONFIG_MACH_SUN7I) || \
144 defined(CONFIG_MACH_SUN8I_R40)
145 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
146 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
147 clock_twi_onoff(2, 1);
148 #elif defined(CONFIG_MACH_SUN5I)
149 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
150 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
151 clock_twi_onoff(2, 1);
152 #elif defined(CONFIG_MACH_SUN6I)
153 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
154 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
155 clock_twi_onoff(2, 1);
156 #elif defined(CONFIG_MACH_SUN8I)
157 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
158 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
159 clock_twi_onoff(2, 1);
160 #elif defined(CONFIG_MACH_SUN50I)
161 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
162 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
163 clock_twi_onoff(2, 1);
167 #ifdef CONFIG_I2C3_ENABLE
168 #if defined(CONFIG_MACH_SUN6I)
169 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
170 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
171 clock_twi_onoff(3, 1);
172 #elif defined(CONFIG_MACH_SUN7I) || \
173 defined(CONFIG_MACH_SUN8I_R40)
174 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
175 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
176 clock_twi_onoff(3, 1);
180 #ifdef CONFIG_I2C4_ENABLE
181 #if defined(CONFIG_MACH_SUN7I) || \
182 defined(CONFIG_MACH_SUN8I_R40)
183 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
184 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
185 clock_twi_onoff(4, 1);
189 #ifdef CONFIG_R_I2C_ENABLE
190 #ifdef CONFIG_MACH_SUN50I
191 clock_twi_onoff(5, 1);
192 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
193 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
195 clock_twi_onoff(5, 1);
196 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
197 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
202 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
203 enum env_location env_get_location(enum env_operation op, int prio)
219 static void mmc_pinmux_setup(int sdc);
222 /* add board specific code here */
225 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
227 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
230 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
231 debug("id_pfr1: 0x%08x\n", id_pfr1);
232 /* Generic Timer Extension available? */
233 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
236 debug("Setting CNTFRQ\n");
239 * CNTFRQ is a secure register, so we will crash if we try to
240 * write this from the non-secure world (read is OK, though).
241 * In case some bootcode has already set the correct value,
242 * we avoid the risk of writing to it.
244 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
245 if (freq != COUNTER_FREQUENCY) {
246 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
247 freq, COUNTER_FREQUENCY);
248 #ifdef CONFIG_NON_SECURE
249 printf("arch timer frequency is wrong, but cannot adjust it\n");
251 asm volatile("mcr p15, 0, %0, c14, c0, 0"
252 : : "r"(COUNTER_FREQUENCY));
256 #endif /* !CONFIG_ARM64 */
258 ret = axp_gpio_init();
262 #ifdef CONFIG_SATAPWR
263 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
264 gpio_request(satapwr_pin, "satapwr");
265 gpio_direction_output(satapwr_pin, 1);
266 /* Give attached sata device time to power-up to avoid link timeouts */
270 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
271 gpio_request(macpwr_pin, "macpwr");
272 gpio_direction_output(macpwr_pin, 1);
277 * Temporary workaround for enabling I2C clocks until proper sunxi DM
278 * clk, reset and pinctrl drivers land.
285 * Temporary workaround for enabling MMC clocks until a sunxi DM
286 * pinctrl driver lands.
288 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
289 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
290 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
292 #endif /* CONFIG_DM_MMC */
294 /* Uses dm gpio code so do this here and not in i2c_init_board() */
295 return soft_i2c_board_init();
299 * On older SoCs the SPL is actually at address zero, so using NULL as
300 * an error value does not work.
302 #define INVALID_SPL_HEADER ((void *)~0UL)
304 static struct boot_file_head * get_spl_header(uint8_t req_version)
306 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
307 uint8_t spl_header_version = spl->spl_signature[3];
309 /* Is there really the SPL header (still) there? */
310 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
311 return INVALID_SPL_HEADER;
313 if (spl_header_version < req_version) {
314 printf("sunxi SPL version mismatch: expected %u, got %u\n",
315 req_version, spl_header_version);
316 return INVALID_SPL_HEADER;
322 #ifdef CONFIG_SPL_LOAD_FIT
323 static const char *get_spl_dt_name(void)
325 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
327 /* Check if there is a DT name stored in the SPL header. */
328 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
329 return (char *)spl + spl->dt_name_offset;
337 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
339 if (spl == INVALID_SPL_HEADER)
340 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
343 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
345 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
346 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
351 #if defined(CONFIG_NAND_SUNXI)
352 static void nand_pinmux_setup(void)
356 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
357 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
359 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
360 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
361 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
363 /* sun4i / sun7i do have a PC23, but it is not used for nand,
364 * only sun7i has a PC24 */
365 #ifdef CONFIG_MACH_SUN7I
366 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
370 static void nand_clock_setup(void)
372 struct sunxi_ccm_reg *const ccm =
373 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
375 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
376 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
377 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
378 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
380 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
383 void board_nand_init(void)
387 #ifndef CONFIG_SPL_BUILD
394 static void mmc_pinmux_setup(int sdc)
397 __maybe_unused int pins;
402 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
403 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
404 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
405 sunxi_gpio_set_drv(pin, 2);
410 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
412 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
413 defined(CONFIG_MACH_SUN8I_R40)
414 if (pins == SUNXI_GPIO_H) {
415 /* SDC1: PH22-PH-27 */
416 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
417 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
418 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
419 sunxi_gpio_set_drv(pin, 2);
423 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
424 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
425 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
426 sunxi_gpio_set_drv(pin, 2);
429 #elif defined(CONFIG_MACH_SUN5I)
431 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
432 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
433 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
434 sunxi_gpio_set_drv(pin, 2);
436 #elif defined(CONFIG_MACH_SUN6I)
438 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
439 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
440 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
441 sunxi_gpio_set_drv(pin, 2);
443 #elif defined(CONFIG_MACH_SUN8I)
444 if (pins == SUNXI_GPIO_D) {
446 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
447 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
448 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
449 sunxi_gpio_set_drv(pin, 2);
453 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
454 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
455 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
456 sunxi_gpio_set_drv(pin, 2);
463 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
465 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
467 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
468 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
469 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
470 sunxi_gpio_set_drv(pin, 2);
472 #elif defined(CONFIG_MACH_SUN5I)
473 if (pins == SUNXI_GPIO_E) {
475 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
476 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
477 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
478 sunxi_gpio_set_drv(pin, 2);
482 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
483 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
484 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
485 sunxi_gpio_set_drv(pin, 2);
488 #elif defined(CONFIG_MACH_SUN6I)
489 if (pins == SUNXI_GPIO_A) {
491 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
492 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
493 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
494 sunxi_gpio_set_drv(pin, 2);
497 /* SDC2: PC6-PC15, PC24 */
498 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
499 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
500 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
501 sunxi_gpio_set_drv(pin, 2);
504 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
505 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
506 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
508 #elif defined(CONFIG_MACH_SUN8I_R40)
509 /* SDC2: PC6-PC15, PC24 */
510 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
511 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
512 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
513 sunxi_gpio_set_drv(pin, 2);
516 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
517 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
518 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
519 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
520 /* SDC2: PC5-PC6, PC8-PC16 */
521 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
522 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
523 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
524 sunxi_gpio_set_drv(pin, 2);
527 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
528 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
529 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
530 sunxi_gpio_set_drv(pin, 2);
532 #elif defined(CONFIG_MACH_SUN50I_H6)
534 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
535 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
536 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
537 sunxi_gpio_set_drv(pin, 2);
539 #elif defined(CONFIG_MACH_SUN9I)
541 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
542 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
543 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
544 sunxi_gpio_set_drv(pin, 2);
550 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
552 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
553 defined(CONFIG_MACH_SUN8I_R40)
555 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
556 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
557 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
558 sunxi_gpio_set_drv(pin, 2);
560 #elif defined(CONFIG_MACH_SUN6I)
561 if (pins == SUNXI_GPIO_A) {
563 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
564 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
565 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
566 sunxi_gpio_set_drv(pin, 2);
569 /* SDC3: PC6-PC15, PC24 */
570 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
571 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
572 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
573 sunxi_gpio_set_drv(pin, 2);
576 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
577 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
578 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
584 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
589 int board_mmc_init(struct bd_info *bis)
591 __maybe_unused struct mmc *mmc0, *mmc1;
593 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
594 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
598 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
599 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
600 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
609 #ifdef CONFIG_SPL_BUILD
611 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
613 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
615 if (spl == INVALID_SPL_HEADER)
618 /* Promote the header version for U-Boot proper, if needed. */
619 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
620 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
622 spl->dram_size = dram_size >> 20;
625 void sunxi_board_init(void)
627 int power_failed = 0;
629 #ifdef CONFIG_SY8106A_POWER
630 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
633 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
634 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
635 defined CONFIG_AXP818_POWER
636 power_failed = axp_init();
638 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
639 defined CONFIG_AXP818_POWER
640 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
642 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
643 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
644 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
645 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
647 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
648 defined CONFIG_AXP818_POWER
649 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
652 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
653 defined CONFIG_AXP818_POWER
654 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
656 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
657 #if !defined(CONFIG_AXP152_POWER)
658 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
660 #ifdef CONFIG_AXP209_POWER
661 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
664 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
665 defined(CONFIG_AXP818_POWER)
666 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
667 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
668 #if !defined CONFIG_AXP809_POWER
669 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
670 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
672 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
673 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
674 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
677 #ifdef CONFIG_AXP818_POWER
678 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
679 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
680 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
683 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
684 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
688 gd->ram_size = sunxi_dram_init();
689 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
693 sunxi_spl_store_dram_size(gd->ram_size);
696 * Only clock up the CPU to full speed if we are reasonably
697 * assured it's being powered with suitable core voltage
700 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
702 printf("Failed to set core voltage! Can't set CPU frequency\n");
706 #ifdef CONFIG_USB_GADGET
707 int g_dnl_board_usb_cable_connected(void)
713 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
715 pr_err("%s: Cannot find USB device\n", __func__);
719 ret = generic_phy_get_by_name(dev, "usb", &phy);
721 pr_err("failed to get %s USB PHY\n", dev->name);
725 ret = generic_phy_init(&phy);
727 pr_debug("failed to init %s USB PHY\n", dev->name);
731 ret = sun4i_usb_phy_vbus_detect(&phy);
733 pr_err("A charger is plugged into the OTG\n");
741 #ifdef CONFIG_SERIAL_TAG
742 void get_board_serial(struct tag_serialnr *serialnr)
745 unsigned long long serial;
747 serial_string = env_get("serial#");
750 serial = simple_strtoull(serial_string, NULL, 16);
752 serialnr->high = (unsigned int) (serial >> 32);
753 serialnr->low = (unsigned int) (serial & 0xffffffff);
762 * Check the SPL header for the "sunxi" variant. If found: parse values
763 * that might have been passed by the loader ("fel" utility), and update
764 * the environment accordingly.
766 static void parse_spl_header(const uint32_t spl_addr)
768 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
770 if (spl == INVALID_SPL_HEADER)
773 if (!spl->fel_script_address)
776 if (spl->fel_uEnv_length != 0) {
778 * data is expected in uEnv.txt compatible format, so "env
779 * import -t" the string(s) at fel_script_address right away.
781 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
782 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
785 /* otherwise assume .scr format (mkimage-type script) */
786 env_set_hex("fel_scriptaddr", spl->fel_script_address);
790 * Note this function gets called multiple times.
791 * It must not make any changes to env variables which already exist.
793 static void setup_environment(const void *fdt)
795 char serial_string[17] = { 0 };
801 ret = sunxi_get_sid(sid);
802 if (ret == 0 && sid[0] != 0) {
804 * The single words 1 - 3 of the SID have quite a few bits
805 * which are the same on many models, so we take a crc32
806 * of all 3 words, to get a more unique value.
808 * Note we only do this on newer SoCs as we cannot change
809 * the algorithm on older SoCs since those have been using
810 * fixed mac-addresses based on only using word 3 for a
811 * long time and changing a fixed mac-address with an
812 * u-boot update is not good.
814 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
815 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
816 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
817 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
820 /* Ensure the NIC specific bytes of the mac are not all 0 */
821 if ((sid[3] & 0xffffff) == 0)
824 for (i = 0; i < 4; i++) {
825 sprintf(ethaddr, "ethernet%d", i);
826 if (!fdt_get_alias(fdt, ethaddr))
830 strcpy(ethaddr, "ethaddr");
832 sprintf(ethaddr, "eth%daddr", i);
834 if (env_get(ethaddr))
837 /* Non OUI / registered MAC address */
838 mac_addr[0] = (i << 4) | 0x02;
839 mac_addr[1] = (sid[0] >> 0) & 0xff;
840 mac_addr[2] = (sid[3] >> 24) & 0xff;
841 mac_addr[3] = (sid[3] >> 16) & 0xff;
842 mac_addr[4] = (sid[3] >> 8) & 0xff;
843 mac_addr[5] = (sid[3] >> 0) & 0xff;
845 eth_env_set_enetaddr(ethaddr, mac_addr);
848 if (!env_get("serial#")) {
849 snprintf(serial_string, sizeof(serial_string),
850 "%08x%08x", sid[0], sid[3]);
852 env_set("serial#", serial_string);
857 int misc_init_r(void)
861 env_set("fel_booted", NULL);
862 env_set("fel_scriptaddr", NULL);
863 env_set("mmc_bootdev", NULL);
865 boot = sunxi_get_boot_device();
866 /* determine if we are running in FEL mode */
867 if (boot == BOOT_DEVICE_BOARD) {
868 env_set("fel_booted", "1");
869 parse_spl_header(SPL_ADDR);
870 /* or if we booted from MMC, and which one */
871 } else if (boot == BOOT_DEVICE_MMC1) {
872 env_set("mmc_bootdev", "0");
873 } else if (boot == BOOT_DEVICE_MMC2) {
874 env_set("mmc_bootdev", "1");
877 setup_environment(gd->fdt_blob);
879 #ifdef CONFIG_USB_ETHER
886 int ft_board_setup(void *blob, struct bd_info *bd)
888 int __maybe_unused r;
891 * Call setup_environment again in case the boot fdt has
892 * ethernet aliases the u-boot copy does not have.
894 setup_environment(blob);
896 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
897 r = sunxi_simplefb_setup(blob);
904 #ifdef CONFIG_SPL_LOAD_FIT
905 int board_fit_config_name_match(const char *name)
907 const char *best_dt_name = get_spl_dt_name();
909 #ifdef CONFIG_DEFAULT_DEVICE_TREE
910 if (best_dt_name == NULL)
911 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
914 if (best_dt_name == NULL) {
915 /* No DT name was provided, so accept the first config. */
918 #ifdef CONFIG_PINE64_DT_SELECTION
919 /* Differentiate the two Pine64 board DTs by their DRAM size. */
920 if (strstr(name, "-pine64") && strstr(best_dt_name, "-pine64")) {
921 if ((gd->ram_size > 512 * 1024 * 1024))
922 return !strstr(name, "plus");
924 return !!strstr(name, "plus");
926 return strcmp(name, best_dt_name);
929 return strcmp(name, best_dt_name);