1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
14 #include <clock_legacy.h>
23 #include <generic-phy.h>
24 #include <phy-sun4i-usb.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/display.h>
28 #include <asm/arch/dram.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/pmic_bus.h>
32 #include <asm/arch/spl.h>
33 #include <asm/global_data.h>
34 #include <linux/delay.h>
35 #include <u-boot/crc.h>
37 #include <asm/armv7.h>
41 #include <u-boot/crc.h>
42 #include <env_internal.h>
43 #include <linux/libfdt.h>
44 #include <fdt_support.h>
49 #include <asm/setup.h>
50 #include <status_led.h>
52 DECLARE_GLOBAL_DATA_PTR;
54 void i2c_init_board(void)
56 #ifdef CONFIG_I2C0_ENABLE
57 #if defined(CONFIG_MACH_SUN4I) || \
58 defined(CONFIG_MACH_SUN5I) || \
59 defined(CONFIG_MACH_SUN7I) || \
60 defined(CONFIG_MACH_SUN8I_R40)
61 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
62 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
63 clock_twi_onoff(0, 1);
64 #elif defined(CONFIG_MACH_SUN6I)
65 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
66 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
67 clock_twi_onoff(0, 1);
68 #elif defined(CONFIG_MACH_SUN8I_V3S)
69 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
70 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
71 clock_twi_onoff(0, 1);
72 #elif defined(CONFIG_MACH_SUN8I)
73 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
74 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
75 clock_twi_onoff(0, 1);
76 #elif defined(CONFIG_MACH_SUN50I)
77 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
78 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
79 clock_twi_onoff(0, 1);
83 #ifdef CONFIG_I2C1_ENABLE
84 #if defined(CONFIG_MACH_SUN4I) || \
85 defined(CONFIG_MACH_SUN7I) || \
86 defined(CONFIG_MACH_SUN8I_R40)
87 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
89 clock_twi_onoff(1, 1);
90 #elif defined(CONFIG_MACH_SUN5I)
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
93 clock_twi_onoff(1, 1);
94 #elif defined(CONFIG_MACH_SUN6I)
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
97 clock_twi_onoff(1, 1);
98 #elif defined(CONFIG_MACH_SUN8I)
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
101 clock_twi_onoff(1, 1);
102 #elif defined(CONFIG_MACH_SUN50I)
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
105 clock_twi_onoff(1, 1);
109 #ifdef CONFIG_I2C2_ENABLE
110 #if defined(CONFIG_MACH_SUN4I) || \
111 defined(CONFIG_MACH_SUN7I) || \
112 defined(CONFIG_MACH_SUN8I_R40)
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
114 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
115 clock_twi_onoff(2, 1);
116 #elif defined(CONFIG_MACH_SUN5I)
117 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
118 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
119 clock_twi_onoff(2, 1);
120 #elif defined(CONFIG_MACH_SUN6I)
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
122 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
123 clock_twi_onoff(2, 1);
124 #elif defined(CONFIG_MACH_SUN8I)
125 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
126 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
127 clock_twi_onoff(2, 1);
128 #elif defined(CONFIG_MACH_SUN50I)
129 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
130 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
131 clock_twi_onoff(2, 1);
135 #ifdef CONFIG_I2C3_ENABLE
136 #if defined(CONFIG_MACH_SUN6I)
137 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
138 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
139 clock_twi_onoff(3, 1);
140 #elif defined(CONFIG_MACH_SUN7I) || \
141 defined(CONFIG_MACH_SUN8I_R40)
142 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
143 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
144 clock_twi_onoff(3, 1);
148 #ifdef CONFIG_I2C4_ENABLE
149 #if defined(CONFIG_MACH_SUN7I) || \
150 defined(CONFIG_MACH_SUN8I_R40)
151 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
152 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
153 clock_twi_onoff(4, 1);
157 #ifdef CONFIG_R_I2C_ENABLE
158 #ifdef CONFIG_MACH_SUN50I
159 clock_twi_onoff(5, 1);
160 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
161 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
162 #elif CONFIG_MACH_SUN50I_H616
163 clock_twi_onoff(5, 1);
164 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
165 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
167 clock_twi_onoff(5, 1);
168 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
169 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
174 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
175 enum env_location env_get_location(enum env_operation op, int prio)
191 static void mmc_pinmux_setup(int sdc);
194 /* add board specific code here */
197 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
199 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
201 #if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
202 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
203 debug("id_pfr1: 0x%08x\n", id_pfr1);
204 /* Generic Timer Extension available? */
205 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
208 debug("Setting CNTFRQ\n");
211 * CNTFRQ is a secure register, so we will crash if we try to
212 * write this from the non-secure world (read is OK, though).
213 * In case some bootcode has already set the correct value,
214 * we avoid the risk of writing to it.
216 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
217 if (freq != COUNTER_FREQUENCY) {
218 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
219 freq, COUNTER_FREQUENCY);
220 #ifdef CONFIG_NON_SECURE
221 printf("arch timer frequency is wrong, but cannot adjust it\n");
223 asm volatile("mcr p15, 0, %0, c14, c0, 0"
224 : : "r"(COUNTER_FREQUENCY));
228 #endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
230 ret = axp_gpio_init();
234 /* strcmp() would look better, but doesn't get optimised away. */
235 if (CONFIG_SATAPWR[0]) {
236 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
237 if (satapwr_pin >= 0) {
238 gpio_request(satapwr_pin, "satapwr");
239 gpio_direction_output(satapwr_pin, 1);
242 * Give the attached SATA device time to power-up
243 * to avoid link timeouts
249 if (CONFIG_MACPWR[0]) {
250 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
251 if (macpwr_pin >= 0) {
252 gpio_request(macpwr_pin, "macpwr");
253 gpio_direction_output(macpwr_pin, 1);
257 #if CONFIG_IS_ENABLED(DM_I2C)
259 * Temporary workaround for enabling I2C clocks until proper sunxi DM
260 * clk, reset and pinctrl drivers land.
267 * Temporary workaround for enabling MMC clocks until a sunxi DM
268 * pinctrl driver lands.
270 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
271 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
272 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
274 #endif /* CONFIG_DM_MMC */
280 * On older SoCs the SPL is actually at address zero, so using NULL as
281 * an error value does not work.
283 #define INVALID_SPL_HEADER ((void *)~0UL)
285 static struct boot_file_head * get_spl_header(uint8_t req_version)
287 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
288 uint8_t spl_header_version = spl->spl_signature[3];
290 /* Is there really the SPL header (still) there? */
291 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
292 return INVALID_SPL_HEADER;
294 if (spl_header_version < req_version) {
295 printf("sunxi SPL version mismatch: expected %u, got %u\n",
296 req_version, spl_header_version);
297 return INVALID_SPL_HEADER;
303 static const char *get_spl_dt_name(void)
305 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
307 /* Check if there is a DT name stored in the SPL header. */
308 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
309 return (char *)spl + spl->dt_name_offset;
316 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
318 if (spl == INVALID_SPL_HEADER)
319 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
322 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
324 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
325 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
330 #if defined(CONFIG_NAND_SUNXI)
331 static void nand_pinmux_setup(void)
335 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
336 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
338 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
339 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
340 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
342 /* sun4i / sun7i do have a PC23, but it is not used for nand,
343 * only sun7i has a PC24 */
344 #ifdef CONFIG_MACH_SUN7I
345 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
349 static void nand_clock_setup(void)
351 struct sunxi_ccm_reg *const ccm =
352 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
354 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
355 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
356 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
357 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
359 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
362 void board_nand_init(void)
366 #ifndef CONFIG_SPL_BUILD
373 static void mmc_pinmux_setup(int sdc)
380 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
381 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
382 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
383 sunxi_gpio_set_drv(pin, 2);
388 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
389 defined(CONFIG_MACH_SUN8I_R40)
390 if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
391 /* SDC1: PH22-PH-27 */
392 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
393 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
394 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
395 sunxi_gpio_set_drv(pin, 2);
399 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
400 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
401 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
402 sunxi_gpio_set_drv(pin, 2);
405 #elif defined(CONFIG_MACH_SUN5I)
407 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
408 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
409 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
410 sunxi_gpio_set_drv(pin, 2);
412 #elif defined(CONFIG_MACH_SUN6I)
414 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
415 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
416 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
417 sunxi_gpio_set_drv(pin, 2);
419 #elif defined(CONFIG_MACH_SUN8I)
421 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
422 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
423 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
424 sunxi_gpio_set_drv(pin, 2);
430 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
432 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
433 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
434 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
435 sunxi_gpio_set_drv(pin, 2);
437 #elif defined(CONFIG_MACH_SUN5I)
439 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
440 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
441 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
442 sunxi_gpio_set_drv(pin, 2);
444 #elif defined(CONFIG_MACH_SUN6I)
445 /* SDC2: PC6-PC15, PC24 */
446 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
447 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
448 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
449 sunxi_gpio_set_drv(pin, 2);
452 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
453 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
454 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
455 #elif defined(CONFIG_MACH_SUN8I_R40)
456 /* SDC2: PC6-PC15, PC24 */
457 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
458 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
459 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
460 sunxi_gpio_set_drv(pin, 2);
463 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
464 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
465 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
466 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
467 /* SDC2: PC5-PC6, PC8-PC16 */
468 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
469 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
470 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
471 sunxi_gpio_set_drv(pin, 2);
474 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
475 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
476 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
477 sunxi_gpio_set_drv(pin, 2);
479 #elif defined(CONFIG_MACH_SUN50I_H6)
481 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
482 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
483 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
484 sunxi_gpio_set_drv(pin, 2);
486 #elif defined(CONFIG_MACH_SUN50I_H616)
487 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
488 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
489 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
491 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
493 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
494 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
495 sunxi_gpio_set_drv(pin, 3);
497 #elif defined(CONFIG_MACH_SUN9I)
499 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
500 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
501 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
502 sunxi_gpio_set_drv(pin, 2);
505 puts("ERROR: No pinmux setup defined for MMC2!\n");
510 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
511 defined(CONFIG_MACH_SUN8I_R40)
513 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
514 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
515 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
516 sunxi_gpio_set_drv(pin, 2);
518 #elif defined(CONFIG_MACH_SUN6I)
519 /* SDC3: PC6-PC15, PC24 */
520 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
521 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
522 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
523 sunxi_gpio_set_drv(pin, 2);
526 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
527 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
528 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
533 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
538 int board_mmc_init(struct bd_info *bis)
540 __maybe_unused struct mmc *mmc0, *mmc1;
542 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
543 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
547 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
548 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
549 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
557 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
558 int mmc_get_env_dev(void)
560 switch (sunxi_get_boot_device()) {
561 case BOOT_DEVICE_MMC1:
563 case BOOT_DEVICE_MMC2:
566 return CONFIG_SYS_MMC_ENV_DEV;
572 #ifdef CONFIG_SPL_BUILD
574 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
576 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
578 if (spl == INVALID_SPL_HEADER)
581 /* Promote the header version for U-Boot proper, if needed. */
582 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
583 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
585 spl->dram_size = dram_size >> 20;
588 void sunxi_board_init(void)
590 int power_failed = 0;
592 #ifdef CONFIG_LED_STATUS
593 if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
597 #ifdef CONFIG_SY8106A_POWER
598 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
601 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
602 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
603 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
604 power_failed = axp_init();
606 if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
609 pmic_bus_read(AXP_POWER_STATUS, &boot_reason);
610 if (boot_reason & AXP_POWER_STATUS_ALDO_IN) {
611 printf("Power on by plug-in, shutting down.\n");
612 pmic_bus_write(0x32, BIT(7));
616 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
617 defined CONFIG_AXP818_POWER
618 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
620 #if !defined(CONFIG_AXP305_POWER)
621 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
622 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
624 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
625 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
627 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
628 defined CONFIG_AXP818_POWER
629 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
632 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
633 defined CONFIG_AXP818_POWER
634 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
636 #if !defined(CONFIG_AXP305_POWER)
637 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
639 #if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
640 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
642 #ifdef CONFIG_AXP209_POWER
643 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
646 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
647 defined(CONFIG_AXP818_POWER)
648 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
649 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
650 #if !defined CONFIG_AXP809_POWER
651 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
652 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
654 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
655 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
656 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
659 #ifdef CONFIG_AXP818_POWER
660 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
661 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
662 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
665 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
666 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
670 gd->ram_size = sunxi_dram_init();
671 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
675 sunxi_spl_store_dram_size(gd->ram_size);
678 * Only clock up the CPU to full speed if we are reasonably
679 * assured it's being powered with suitable core voltage
682 clock_set_pll1(get_board_sys_clk());
684 printf("Failed to set core voltage! Can't set CPU frequency\n");
688 #ifdef CONFIG_USB_GADGET
689 int g_dnl_board_usb_cable_connected(void)
695 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
697 pr_err("%s: Cannot find USB device\n", __func__);
701 ret = generic_phy_get_by_name(dev, "usb", &phy);
703 pr_err("failed to get %s USB PHY\n", dev->name);
707 ret = generic_phy_init(&phy);
709 pr_debug("failed to init %s USB PHY\n", dev->name);
713 return sun4i_usb_phy_vbus_detect(&phy);
717 #ifdef CONFIG_SERIAL_TAG
718 void get_board_serial(struct tag_serialnr *serialnr)
721 unsigned long long serial;
723 serial_string = env_get("serial#");
726 serial = simple_strtoull(serial_string, NULL, 16);
728 serialnr->high = (unsigned int) (serial >> 32);
729 serialnr->low = (unsigned int) (serial & 0xffffffff);
738 * Check the SPL header for the "sunxi" variant. If found: parse values
739 * that might have been passed by the loader ("fel" utility), and update
740 * the environment accordingly.
742 static void parse_spl_header(const uint32_t spl_addr)
744 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
746 if (spl == INVALID_SPL_HEADER)
749 if (!spl->fel_script_address)
752 if (spl->fel_uEnv_length != 0) {
754 * data is expected in uEnv.txt compatible format, so "env
755 * import -t" the string(s) at fel_script_address right away.
757 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
758 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
761 /* otherwise assume .scr format (mkimage-type script) */
762 env_set_hex("fel_scriptaddr", spl->fel_script_address);
765 static bool get_unique_sid(unsigned int *sid)
767 if (sunxi_get_sid(sid) != 0)
774 * The single words 1 - 3 of the SID have quite a few bits
775 * which are the same on many models, so we take a crc32
776 * of all 3 words, to get a more unique value.
778 * Note we only do this on newer SoCs as we cannot change
779 * the algorithm on older SoCs since those have been using
780 * fixed mac-addresses based on only using word 3 for a
781 * long time and changing a fixed mac-address with an
782 * u-boot update is not good.
784 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
785 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
786 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
787 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
790 /* Ensure the NIC specific bytes of the mac are not all 0 */
791 if ((sid[3] & 0xffffff) == 0)
798 * Note this function gets called multiple times.
799 * It must not make any changes to env variables which already exist.
801 static void setup_environment(const void *fdt)
803 char serial_string[17] = { 0 };
809 if (!get_unique_sid(sid))
812 for (i = 0; i < 4; i++) {
813 sprintf(ethaddr, "ethernet%d", i);
814 if (!fdt_get_alias(fdt, ethaddr))
818 strcpy(ethaddr, "ethaddr");
820 sprintf(ethaddr, "eth%daddr", i);
822 if (env_get(ethaddr))
825 /* Non OUI / registered MAC address */
826 mac_addr[0] = (i << 4) | 0x02;
827 mac_addr[1] = (sid[0] >> 0) & 0xff;
828 mac_addr[2] = (sid[3] >> 24) & 0xff;
829 mac_addr[3] = (sid[3] >> 16) & 0xff;
830 mac_addr[4] = (sid[3] >> 8) & 0xff;
831 mac_addr[5] = (sid[3] >> 0) & 0xff;
833 eth_env_set_enetaddr(ethaddr, mac_addr);
836 if (!env_get("serial#")) {
837 snprintf(serial_string, sizeof(serial_string),
838 "%08x%08x", sid[0], sid[3]);
840 env_set("serial#", serial_string);
844 int misc_init_r(void)
846 const char *spl_dt_name;
849 env_set("fel_booted", NULL);
850 env_set("fel_scriptaddr", NULL);
851 env_set("mmc_bootdev", NULL);
853 boot = sunxi_get_boot_device();
854 /* determine if we are running in FEL mode */
855 if (boot == BOOT_DEVICE_BOARD) {
856 env_set("fel_booted", "1");
857 parse_spl_header(SPL_ADDR);
858 /* or if we booted from MMC, and which one */
859 } else if (boot == BOOT_DEVICE_MMC1) {
860 env_set("mmc_bootdev", "0");
861 } else if (boot == BOOT_DEVICE_MMC2) {
862 env_set("mmc_bootdev", "1");
865 /* Set fdtfile to match the FIT configuration chosen in SPL. */
866 spl_dt_name = get_spl_dt_name();
868 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
871 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
872 env_set("fdtfile", str);
875 setup_environment(gd->fdt_blob);
880 int board_late_init(void)
882 #ifdef CONFIG_USB_ETHER
889 static void bluetooth_dt_fixup(void *blob)
891 /* Some devices ship with a Bluetooth controller default address.
892 * Set a valid address through the device tree.
894 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
898 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
901 if (eth_env_get_enetaddr("bdaddr", tmp)) {
902 /* Convert between the binary formats of the corresponding stacks */
903 for (i = 0; i < ETH_ALEN; ++i)
904 bdaddr[i] = tmp[ETH_ALEN - i - 1];
906 if (!get_unique_sid(sid))
909 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
910 bdaddr[1] = (sid[3] >> 8) & 0xff;
911 bdaddr[2] = (sid[3] >> 16) & 0xff;
912 bdaddr[3] = (sid[3] >> 24) & 0xff;
913 bdaddr[4] = (sid[0] >> 0) & 0xff;
917 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
918 "local-bd-address", bdaddr, ETH_ALEN, 1);
921 int ft_board_setup(void *blob, struct bd_info *bd)
923 int __maybe_unused r;
926 * Call setup_environment and fdt_fixup_ethernet again
927 * in case the boot fdt has ethernet aliases the u-boot
928 * copy does not have.
930 setup_environment(blob);
931 fdt_fixup_ethernet(blob);
933 bluetooth_dt_fixup(blob);
935 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
936 r = sunxi_simplefb_setup(blob);
943 #ifdef CONFIG_SPL_LOAD_FIT
945 static void set_spl_dt_name(const char *name)
947 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
949 if (spl == INVALID_SPL_HEADER)
952 /* Promote the header version for U-Boot proper, if needed. */
953 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
954 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
956 strcpy((char *)&spl->string_pool, name);
957 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
960 int board_fit_config_name_match(const char *name)
962 const char *best_dt_name = get_spl_dt_name();
965 #ifdef CONFIG_DEFAULT_DEVICE_TREE
966 if (best_dt_name == NULL)
967 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
970 if (best_dt_name == NULL) {
971 /* No DT name was provided, so accept the first config. */
974 #ifdef CONFIG_PINE64_DT_SELECTION
975 if (strstr(best_dt_name, "-pine64-plus")) {
976 /* Differentiate the Pine A64 boards by their DRAM size. */
977 if ((gd->ram_size == 512 * 1024 * 1024))
978 best_dt_name = "sun50i-a64-pine64";
981 #ifdef CONFIG_PINEPHONE_DT_SELECTION
982 if (strstr(best_dt_name, "-pinephone")) {
983 /* Differentiate the PinePhone revisions by GPIO inputs. */
984 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
985 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
986 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
989 /* PL6 is pulled low by the modem on v1.2. */
990 if (gpio_get_value(SUNXI_GPL(6)) == 0)
991 best_dt_name = "sun50i-a64-pinephone-1.2";
993 best_dt_name = "sun50i-a64-pinephone-1.1";
995 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
996 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
997 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
1001 ret = strcmp(name, best_dt_name);
1004 * If one of the FIT configurations matches the most accurate DT name,
1005 * update the SPL header to provide that DT name to U-Boot proper.
1008 set_spl_dt_name(best_dt_name);