1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
17 #include <generic-phy.h>
18 #include <phy-sun4i-usb.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/display.h>
22 #include <asm/arch/dram.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/mmc.h>
25 #include <asm/arch/spl.h>
26 #include <asm/arch/usb_phy.h>
28 #include <asm/armv7.h>
33 #include <environment.h>
34 #include <linux/libfdt.h>
39 #include <asm/setup.h>
41 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
42 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
43 int soft_i2c_gpio_sda;
44 int soft_i2c_gpio_scl;
46 static int soft_i2c_board_init(void)
50 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
51 if (soft_i2c_gpio_sda < 0) {
52 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
53 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
54 return soft_i2c_gpio_sda;
56 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
58 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
59 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
63 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
64 if (soft_i2c_gpio_scl < 0) {
65 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
66 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
67 return soft_i2c_gpio_scl;
69 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
71 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
72 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
79 static int soft_i2c_board_init(void) { return 0; }
82 DECLARE_GLOBAL_DATA_PTR;
84 void i2c_init_board(void)
86 #ifdef CONFIG_I2C0_ENABLE
87 #if defined(CONFIG_MACH_SUN4I) || \
88 defined(CONFIG_MACH_SUN5I) || \
89 defined(CONFIG_MACH_SUN7I) || \
90 defined(CONFIG_MACH_SUN8I_R40)
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
93 clock_twi_onoff(0, 1);
94 #elif defined(CONFIG_MACH_SUN6I)
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
97 clock_twi_onoff(0, 1);
98 #elif defined(CONFIG_MACH_SUN8I)
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
101 clock_twi_onoff(0, 1);
105 #ifdef CONFIG_I2C1_ENABLE
106 #if defined(CONFIG_MACH_SUN4I) || \
107 defined(CONFIG_MACH_SUN7I) || \
108 defined(CONFIG_MACH_SUN8I_R40)
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
111 clock_twi_onoff(1, 1);
112 #elif defined(CONFIG_MACH_SUN5I)
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
114 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
115 clock_twi_onoff(1, 1);
116 #elif defined(CONFIG_MACH_SUN6I)
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
118 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
119 clock_twi_onoff(1, 1);
120 #elif defined(CONFIG_MACH_SUN8I)
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
122 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
123 clock_twi_onoff(1, 1);
127 #ifdef CONFIG_I2C2_ENABLE
128 #if defined(CONFIG_MACH_SUN4I) || \
129 defined(CONFIG_MACH_SUN7I) || \
130 defined(CONFIG_MACH_SUN8I_R40)
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
132 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
133 clock_twi_onoff(2, 1);
134 #elif defined(CONFIG_MACH_SUN5I)
135 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
136 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
137 clock_twi_onoff(2, 1);
138 #elif defined(CONFIG_MACH_SUN6I)
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
140 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
141 clock_twi_onoff(2, 1);
142 #elif defined(CONFIG_MACH_SUN8I)
143 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
144 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
145 clock_twi_onoff(2, 1);
149 #ifdef CONFIG_I2C3_ENABLE
150 #if defined(CONFIG_MACH_SUN6I)
151 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
152 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
153 clock_twi_onoff(3, 1);
154 #elif defined(CONFIG_MACH_SUN7I) || \
155 defined(CONFIG_MACH_SUN8I_R40)
156 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
157 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
158 clock_twi_onoff(3, 1);
162 #ifdef CONFIG_I2C4_ENABLE
163 #if defined(CONFIG_MACH_SUN7I) || \
164 defined(CONFIG_MACH_SUN8I_R40)
165 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
166 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
167 clock_twi_onoff(4, 1);
171 #ifdef CONFIG_R_I2C_ENABLE
172 clock_twi_onoff(5, 1);
173 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
174 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
178 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
179 enum env_location env_get_location(enum env_operation op, int prio)
194 /* add board specific code here */
197 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
199 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
202 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
203 debug("id_pfr1: 0x%08x\n", id_pfr1);
204 /* Generic Timer Extension available? */
205 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
208 debug("Setting CNTFRQ\n");
211 * CNTFRQ is a secure register, so we will crash if we try to
212 * write this from the non-secure world (read is OK, though).
213 * In case some bootcode has already set the correct value,
214 * we avoid the risk of writing to it.
216 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
217 if (freq != COUNTER_FREQUENCY) {
218 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
219 freq, COUNTER_FREQUENCY);
220 #ifdef CONFIG_NON_SECURE
221 printf("arch timer frequency is wrong, but cannot adjust it\n");
223 asm volatile("mcr p15, 0, %0, c14, c0, 0"
224 : : "r"(COUNTER_FREQUENCY));
228 #endif /* !CONFIG_ARM64 */
230 ret = axp_gpio_init();
234 #ifdef CONFIG_SATAPWR
235 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
236 gpio_request(satapwr_pin, "satapwr");
237 gpio_direction_output(satapwr_pin, 1);
238 /* Give attached sata device time to power-up to avoid link timeouts */
242 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
243 gpio_request(macpwr_pin, "macpwr");
244 gpio_direction_output(macpwr_pin, 1);
249 * Temporary workaround for enabling I2C clocks until proper sunxi DM
250 * clk, reset and pinctrl drivers land.
255 /* Uses dm gpio code so do this here and not in i2c_init_board() */
256 return soft_i2c_board_init();
261 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
266 #if defined(CONFIG_NAND_SUNXI)
267 static void nand_pinmux_setup(void)
271 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
272 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
274 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
275 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
276 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
278 /* sun4i / sun7i do have a PC23, but it is not used for nand,
279 * only sun7i has a PC24 */
280 #ifdef CONFIG_MACH_SUN7I
281 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
285 static void nand_clock_setup(void)
287 struct sunxi_ccm_reg *const ccm =
288 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
290 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
291 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
292 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
293 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
295 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
298 void board_nand_init(void)
302 #ifndef CONFIG_SPL_BUILD
309 static void mmc_pinmux_setup(int sdc)
312 __maybe_unused int pins;
317 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
318 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
319 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
320 sunxi_gpio_set_drv(pin, 2);
325 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
327 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
328 defined(CONFIG_MACH_SUN8I_R40)
329 if (pins == SUNXI_GPIO_H) {
330 /* SDC1: PH22-PH-27 */
331 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
332 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
333 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
334 sunxi_gpio_set_drv(pin, 2);
338 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
339 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
340 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
341 sunxi_gpio_set_drv(pin, 2);
344 #elif defined(CONFIG_MACH_SUN5I)
346 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
347 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
348 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
349 sunxi_gpio_set_drv(pin, 2);
351 #elif defined(CONFIG_MACH_SUN6I)
353 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
354 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
355 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
356 sunxi_gpio_set_drv(pin, 2);
358 #elif defined(CONFIG_MACH_SUN8I)
359 if (pins == SUNXI_GPIO_D) {
361 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
362 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
363 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
364 sunxi_gpio_set_drv(pin, 2);
368 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
369 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
370 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
371 sunxi_gpio_set_drv(pin, 2);
378 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
380 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
382 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
383 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
384 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
385 sunxi_gpio_set_drv(pin, 2);
387 #elif defined(CONFIG_MACH_SUN5I)
388 if (pins == SUNXI_GPIO_E) {
390 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
391 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
392 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
393 sunxi_gpio_set_drv(pin, 2);
397 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
398 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
399 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
400 sunxi_gpio_set_drv(pin, 2);
403 #elif defined(CONFIG_MACH_SUN6I)
404 if (pins == SUNXI_GPIO_A) {
406 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
407 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
408 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
409 sunxi_gpio_set_drv(pin, 2);
412 /* SDC2: PC6-PC15, PC24 */
413 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
414 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
415 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
416 sunxi_gpio_set_drv(pin, 2);
419 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
420 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
421 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
423 #elif defined(CONFIG_MACH_SUN8I_R40)
424 /* SDC2: PC6-PC15, PC24 */
425 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
426 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
427 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
428 sunxi_gpio_set_drv(pin, 2);
431 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
432 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
433 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
434 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
435 /* SDC2: PC5-PC6, PC8-PC16 */
436 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
437 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
438 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
439 sunxi_gpio_set_drv(pin, 2);
442 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
443 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
444 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
445 sunxi_gpio_set_drv(pin, 2);
447 #elif defined(CONFIG_MACH_SUN9I)
449 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
450 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
451 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
452 sunxi_gpio_set_drv(pin, 2);
458 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
460 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
461 defined(CONFIG_MACH_SUN8I_R40)
463 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
464 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
465 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
466 sunxi_gpio_set_drv(pin, 2);
468 #elif defined(CONFIG_MACH_SUN6I)
469 if (pins == SUNXI_GPIO_A) {
471 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
472 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
473 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
474 sunxi_gpio_set_drv(pin, 2);
477 /* SDC3: PC6-PC15, PC24 */
478 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
479 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
480 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
481 sunxi_gpio_set_drv(pin, 2);
484 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
485 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
486 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
492 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
497 int board_mmc_init(bd_t *bis)
499 __maybe_unused struct mmc *mmc0, *mmc1;
500 __maybe_unused char buf[512];
502 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
503 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
507 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
508 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
509 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
518 #ifdef CONFIG_SPL_BUILD
519 void sunxi_board_init(void)
521 int power_failed = 0;
523 #ifdef CONFIG_SY8106A_POWER
524 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
527 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
528 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
529 defined CONFIG_AXP818_POWER
530 power_failed = axp_init();
532 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
533 defined CONFIG_AXP818_POWER
534 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
536 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
537 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
538 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
539 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
541 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
542 defined CONFIG_AXP818_POWER
543 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
546 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
547 defined CONFIG_AXP818_POWER
548 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
550 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
551 #if !defined(CONFIG_AXP152_POWER)
552 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
554 #ifdef CONFIG_AXP209_POWER
555 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
558 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
559 defined(CONFIG_AXP818_POWER)
560 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
561 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
562 #if !defined CONFIG_AXP809_POWER
563 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
564 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
566 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
567 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
568 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
571 #ifdef CONFIG_AXP818_POWER
572 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
573 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
574 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
577 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
578 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
582 gd->ram_size = sunxi_dram_init();
583 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
588 * Only clock up the CPU to full speed if we are reasonably
589 * assured it's being powered with suitable core voltage
592 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
594 printf("Failed to set core voltage! Can't set CPU frequency\n");
598 #ifdef CONFIG_USB_GADGET
599 int g_dnl_board_usb_cable_connected(void)
605 ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev);
607 pr_err("%s: Cannot find USB device\n", __func__);
611 ret = generic_phy_get_by_name(dev, "usb", &phy);
613 pr_err("failed to get %s USB PHY\n", dev->name);
617 ret = generic_phy_init(&phy);
619 pr_err("failed to init %s USB PHY\n", dev->name);
623 ret = sun4i_usb_phy_vbus_detect(&phy);
625 pr_err("A charger is plugged into the OTG\n");
633 #ifdef CONFIG_SERIAL_TAG
634 void get_board_serial(struct tag_serialnr *serialnr)
637 unsigned long long serial;
639 serial_string = env_get("serial#");
642 serial = simple_strtoull(serial_string, NULL, 16);
644 serialnr->high = (unsigned int) (serial >> 32);
645 serialnr->low = (unsigned int) (serial & 0xffffffff);
654 * Check the SPL header for the "sunxi" variant. If found: parse values
655 * that might have been passed by the loader ("fel" utility), and update
656 * the environment accordingly.
658 static void parse_spl_header(const uint32_t spl_addr)
660 struct boot_file_head *spl = (void *)(ulong)spl_addr;
661 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
662 return; /* signature mismatch, no usable header */
664 uint8_t spl_header_version = spl->spl_signature[3];
665 if (spl_header_version != SPL_HEADER_VERSION) {
666 printf("sunxi SPL version mismatch: expected %u, got %u\n",
667 SPL_HEADER_VERSION, spl_header_version);
670 if (!spl->fel_script_address)
673 if (spl->fel_uEnv_length != 0) {
675 * data is expected in uEnv.txt compatible format, so "env
676 * import -t" the string(s) at fel_script_address right away.
678 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
679 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
682 /* otherwise assume .scr format (mkimage-type script) */
683 env_set_hex("fel_scriptaddr", spl->fel_script_address);
687 * Note this function gets called multiple times.
688 * It must not make any changes to env variables which already exist.
690 static void setup_environment(const void *fdt)
692 char serial_string[17] = { 0 };
698 ret = sunxi_get_sid(sid);
699 if (ret == 0 && sid[0] != 0) {
701 * The single words 1 - 3 of the SID have quite a few bits
702 * which are the same on many models, so we take a crc32
703 * of all 3 words, to get a more unique value.
705 * Note we only do this on newer SoCs as we cannot change
706 * the algorithm on older SoCs since those have been using
707 * fixed mac-addresses based on only using word 3 for a
708 * long time and changing a fixed mac-address with an
709 * u-boot update is not good.
711 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
712 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
713 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
714 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
717 /* Ensure the NIC specific bytes of the mac are not all 0 */
718 if ((sid[3] & 0xffffff) == 0)
721 for (i = 0; i < 4; i++) {
722 sprintf(ethaddr, "ethernet%d", i);
723 if (!fdt_get_alias(fdt, ethaddr))
727 strcpy(ethaddr, "ethaddr");
729 sprintf(ethaddr, "eth%daddr", i);
731 if (env_get(ethaddr))
734 /* Non OUI / registered MAC address */
735 mac_addr[0] = (i << 4) | 0x02;
736 mac_addr[1] = (sid[0] >> 0) & 0xff;
737 mac_addr[2] = (sid[3] >> 24) & 0xff;
738 mac_addr[3] = (sid[3] >> 16) & 0xff;
739 mac_addr[4] = (sid[3] >> 8) & 0xff;
740 mac_addr[5] = (sid[3] >> 0) & 0xff;
742 eth_env_set_enetaddr(ethaddr, mac_addr);
745 if (!env_get("serial#")) {
746 snprintf(serial_string, sizeof(serial_string),
747 "%08x%08x", sid[0], sid[3]);
749 env_set("serial#", serial_string);
754 int misc_init_r(void)
756 __maybe_unused int ret;
759 env_set("fel_booted", NULL);
760 env_set("fel_scriptaddr", NULL);
761 env_set("mmc_bootdev", NULL);
763 boot = sunxi_get_boot_device();
764 /* determine if we are running in FEL mode */
765 if (boot == BOOT_DEVICE_BOARD) {
766 env_set("fel_booted", "1");
767 parse_spl_header(SPL_ADDR);
768 /* or if we booted from MMC, and which one */
769 } else if (boot == BOOT_DEVICE_MMC1) {
770 env_set("mmc_bootdev", "0");
771 } else if (boot == BOOT_DEVICE_MMC2) {
772 env_set("mmc_bootdev", "1");
775 setup_environment(gd->fdt_blob);
777 #ifndef CONFIG_MACH_SUN9I
778 ret = sunxi_usb_phy_probe();
783 #ifdef CONFIG_USB_ETHER
790 int ft_board_setup(void *blob, bd_t *bd)
792 int __maybe_unused r;
795 * Call setup_environment again in case the boot fdt has
796 * ethernet aliases the u-boot copy does not have.
798 setup_environment(blob);
800 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
801 r = sunxi_simplefb_setup(blob);
808 #ifdef CONFIG_SPL_LOAD_FIT
809 int board_fit_config_name_match(const char *name)
811 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
812 const char *cmp_str = (void *)(ulong)SPL_ADDR;
814 /* Check if there is a DT name stored in the SPL header and use that. */
815 if (spl->dt_name_offset) {
816 cmp_str += spl->dt_name_offset;
818 #ifdef CONFIG_DEFAULT_DEVICE_TREE
819 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
825 /* Differentiate the two Pine64 board DTs by their DRAM size. */
826 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
827 if ((gd->ram_size > 512 * 1024 * 1024))
828 return !strstr(name, "plus");
830 return !!strstr(name, "plus");
832 return strcmp(name, cmp_str);