1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
14 #include <clock_legacy.h>
23 #include <generic-phy.h>
24 #include <phy-sun4i-usb.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/display.h>
28 #include <asm/arch/dram.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/spl.h>
32 #include <asm/global_data.h>
33 #include <linux/delay.h>
34 #include <u-boot/crc.h>
36 #include <asm/armv7.h>
40 #include <u-boot/crc.h>
41 #include <env_internal.h>
42 #include <linux/libfdt.h>
43 #include <fdt_support.h>
48 #include <asm/setup.h>
49 #include <status_led.h>
51 DECLARE_GLOBAL_DATA_PTR;
53 void i2c_init_board(void)
55 #ifdef CONFIG_I2C0_ENABLE
56 #if defined(CONFIG_MACH_SUN4I) || \
57 defined(CONFIG_MACH_SUN5I) || \
58 defined(CONFIG_MACH_SUN7I) || \
59 defined(CONFIG_MACH_SUN8I_R40)
60 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
61 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
62 clock_twi_onoff(0, 1);
63 #elif defined(CONFIG_MACH_SUN6I)
64 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
65 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
66 clock_twi_onoff(0, 1);
67 #elif defined(CONFIG_MACH_SUN8I_V3S)
68 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
69 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
70 clock_twi_onoff(0, 1);
71 #elif defined(CONFIG_MACH_SUN8I)
72 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
73 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
74 clock_twi_onoff(0, 1);
75 #elif defined(CONFIG_MACH_SUN50I)
76 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
77 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
78 clock_twi_onoff(0, 1);
82 #ifdef CONFIG_I2C1_ENABLE
83 #if defined(CONFIG_MACH_SUN4I) || \
84 defined(CONFIG_MACH_SUN7I) || \
85 defined(CONFIG_MACH_SUN8I_R40)
86 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
87 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
88 clock_twi_onoff(1, 1);
89 #elif defined(CONFIG_MACH_SUN5I)
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
92 clock_twi_onoff(1, 1);
93 #elif defined(CONFIG_MACH_SUN6I)
94 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
96 clock_twi_onoff(1, 1);
97 #elif defined(CONFIG_MACH_SUN8I)
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
100 clock_twi_onoff(1, 1);
101 #elif defined(CONFIG_MACH_SUN50I)
102 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
104 clock_twi_onoff(1, 1);
108 #ifdef CONFIG_I2C2_ENABLE
109 #if defined(CONFIG_MACH_SUN4I) || \
110 defined(CONFIG_MACH_SUN7I) || \
111 defined(CONFIG_MACH_SUN8I_R40)
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
114 clock_twi_onoff(2, 1);
115 #elif defined(CONFIG_MACH_SUN5I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
117 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
118 clock_twi_onoff(2, 1);
119 #elif defined(CONFIG_MACH_SUN6I)
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
122 clock_twi_onoff(2, 1);
123 #elif defined(CONFIG_MACH_SUN8I)
124 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
125 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
126 clock_twi_onoff(2, 1);
127 #elif defined(CONFIG_MACH_SUN50I)
128 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
129 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
130 clock_twi_onoff(2, 1);
134 #ifdef CONFIG_I2C3_ENABLE
135 #if defined(CONFIG_MACH_SUN6I)
136 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
137 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
138 clock_twi_onoff(3, 1);
139 #elif defined(CONFIG_MACH_SUN7I) || \
140 defined(CONFIG_MACH_SUN8I_R40)
141 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
142 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
143 clock_twi_onoff(3, 1);
147 #ifdef CONFIG_I2C4_ENABLE
148 #if defined(CONFIG_MACH_SUN7I) || \
149 defined(CONFIG_MACH_SUN8I_R40)
150 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
151 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
152 clock_twi_onoff(4, 1);
156 #ifdef CONFIG_R_I2C_ENABLE
157 #ifdef CONFIG_MACH_SUN50I
158 clock_twi_onoff(5, 1);
159 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
160 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
161 #elif CONFIG_MACH_SUN50I_H616
162 clock_twi_onoff(5, 1);
163 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
164 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
166 clock_twi_onoff(5, 1);
167 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
168 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
173 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
174 enum env_location env_get_location(enum env_operation op, int prio)
190 static void mmc_pinmux_setup(int sdc);
193 /* add board specific code here */
196 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
198 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
201 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
202 debug("id_pfr1: 0x%08x\n", id_pfr1);
203 /* Generic Timer Extension available? */
204 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
207 debug("Setting CNTFRQ\n");
210 * CNTFRQ is a secure register, so we will crash if we try to
211 * write this from the non-secure world (read is OK, though).
212 * In case some bootcode has already set the correct value,
213 * we avoid the risk of writing to it.
215 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
216 if (freq != COUNTER_FREQUENCY) {
217 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
218 freq, COUNTER_FREQUENCY);
219 #ifdef CONFIG_NON_SECURE
220 printf("arch timer frequency is wrong, but cannot adjust it\n");
222 asm volatile("mcr p15, 0, %0, c14, c0, 0"
223 : : "r"(COUNTER_FREQUENCY));
227 #endif /* !CONFIG_ARM64 */
229 ret = axp_gpio_init();
233 /* strcmp() would look better, but doesn't get optimised away. */
234 if (CONFIG_SATAPWR[0]) {
235 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
236 if (satapwr_pin >= 0) {
237 gpio_request(satapwr_pin, "satapwr");
238 gpio_direction_output(satapwr_pin, 1);
241 * Give the attached SATA device time to power-up
242 * to avoid link timeouts
248 if (CONFIG_MACPWR[0]) {
249 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
250 if (macpwr_pin >= 0) {
251 gpio_request(macpwr_pin, "macpwr");
252 gpio_direction_output(macpwr_pin, 1);
256 #if CONFIG_IS_ENABLED(DM_I2C)
258 * Temporary workaround for enabling I2C clocks until proper sunxi DM
259 * clk, reset and pinctrl drivers land.
266 * Temporary workaround for enabling MMC clocks until a sunxi DM
267 * pinctrl driver lands.
269 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
270 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
271 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
273 #endif /* CONFIG_DM_MMC */
279 * On older SoCs the SPL is actually at address zero, so using NULL as
280 * an error value does not work.
282 #define INVALID_SPL_HEADER ((void *)~0UL)
284 static struct boot_file_head * get_spl_header(uint8_t req_version)
286 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
287 uint8_t spl_header_version = spl->spl_signature[3];
289 /* Is there really the SPL header (still) there? */
290 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
291 return INVALID_SPL_HEADER;
293 if (spl_header_version < req_version) {
294 printf("sunxi SPL version mismatch: expected %u, got %u\n",
295 req_version, spl_header_version);
296 return INVALID_SPL_HEADER;
302 static const char *get_spl_dt_name(void)
304 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
306 /* Check if there is a DT name stored in the SPL header. */
307 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
308 return (char *)spl + spl->dt_name_offset;
315 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
317 if (spl == INVALID_SPL_HEADER)
318 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
321 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
323 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
324 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
329 #if defined(CONFIG_NAND_SUNXI)
330 static void nand_pinmux_setup(void)
334 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
335 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
337 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
338 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
339 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
341 /* sun4i / sun7i do have a PC23, but it is not used for nand,
342 * only sun7i has a PC24 */
343 #ifdef CONFIG_MACH_SUN7I
344 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
348 static void nand_clock_setup(void)
350 struct sunxi_ccm_reg *const ccm =
351 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
353 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
354 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
355 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
356 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
358 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
361 void board_nand_init(void)
365 #ifndef CONFIG_SPL_BUILD
372 static void mmc_pinmux_setup(int sdc)
379 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
380 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
381 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
382 sunxi_gpio_set_drv(pin, 2);
387 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
388 defined(CONFIG_MACH_SUN8I_R40)
389 if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
390 /* SDC1: PH22-PH-27 */
391 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
392 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
393 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
394 sunxi_gpio_set_drv(pin, 2);
398 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
399 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
400 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
401 sunxi_gpio_set_drv(pin, 2);
404 #elif defined(CONFIG_MACH_SUN5I)
406 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
407 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
408 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
409 sunxi_gpio_set_drv(pin, 2);
411 #elif defined(CONFIG_MACH_SUN6I)
413 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
414 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
415 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
416 sunxi_gpio_set_drv(pin, 2);
418 #elif defined(CONFIG_MACH_SUN8I)
420 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
421 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
422 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
423 sunxi_gpio_set_drv(pin, 2);
429 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
431 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
432 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
433 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
434 sunxi_gpio_set_drv(pin, 2);
436 #elif defined(CONFIG_MACH_SUN5I)
438 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
439 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
440 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
441 sunxi_gpio_set_drv(pin, 2);
443 #elif defined(CONFIG_MACH_SUN6I)
444 /* SDC2: PC6-PC15, PC24 */
445 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
446 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
447 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
448 sunxi_gpio_set_drv(pin, 2);
451 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
452 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
453 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
454 #elif defined(CONFIG_MACH_SUN8I_R40)
455 /* SDC2: PC6-PC15, PC24 */
456 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
457 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
458 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
459 sunxi_gpio_set_drv(pin, 2);
462 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
463 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
464 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
465 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
466 /* SDC2: PC5-PC6, PC8-PC16 */
467 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
468 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
469 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
470 sunxi_gpio_set_drv(pin, 2);
473 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
474 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
475 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
476 sunxi_gpio_set_drv(pin, 2);
478 #elif defined(CONFIG_MACH_SUN50I_H6)
480 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
481 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
482 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
483 sunxi_gpio_set_drv(pin, 2);
485 #elif defined(CONFIG_MACH_SUN50I_H616)
486 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
487 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
488 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
490 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
492 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
493 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
494 sunxi_gpio_set_drv(pin, 3);
496 #elif defined(CONFIG_MACH_SUN9I)
498 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
499 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
500 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
501 sunxi_gpio_set_drv(pin, 2);
504 puts("ERROR: No pinmux setup defined for MMC2!\n");
509 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
510 defined(CONFIG_MACH_SUN8I_R40)
512 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
513 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
514 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
515 sunxi_gpio_set_drv(pin, 2);
517 #elif defined(CONFIG_MACH_SUN6I)
518 /* SDC3: PC6-PC15, PC24 */
519 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
520 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
521 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
522 sunxi_gpio_set_drv(pin, 2);
525 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
526 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
527 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
532 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
537 int board_mmc_init(struct bd_info *bis)
539 __maybe_unused struct mmc *mmc0, *mmc1;
541 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
542 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
546 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
547 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
548 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
556 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
557 int mmc_get_env_dev(void)
559 switch (sunxi_get_boot_device()) {
560 case BOOT_DEVICE_MMC1:
562 case BOOT_DEVICE_MMC2:
565 return CONFIG_SYS_MMC_ENV_DEV;
571 #ifdef CONFIG_SPL_BUILD
573 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
575 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
577 if (spl == INVALID_SPL_HEADER)
580 /* Promote the header version for U-Boot proper, if needed. */
581 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
582 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
584 spl->dram_size = dram_size >> 20;
587 void sunxi_board_init(void)
589 int power_failed = 0;
591 #ifdef CONFIG_LED_STATUS
592 if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
596 #ifdef CONFIG_SY8106A_POWER
597 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
600 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
601 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
602 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
603 power_failed = axp_init();
605 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
606 defined CONFIG_AXP818_POWER
607 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
609 #if !defined(CONFIG_AXP305_POWER)
610 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
611 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
613 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
614 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
616 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
617 defined CONFIG_AXP818_POWER
618 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
621 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
622 defined CONFIG_AXP818_POWER
623 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
625 #if !defined(CONFIG_AXP305_POWER)
626 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
628 #if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
629 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
631 #ifdef CONFIG_AXP209_POWER
632 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
635 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
636 defined(CONFIG_AXP818_POWER)
637 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
638 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
639 #if !defined CONFIG_AXP809_POWER
640 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
641 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
643 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
644 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
645 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
648 #ifdef CONFIG_AXP818_POWER
649 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
650 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
651 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
654 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
655 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
659 gd->ram_size = sunxi_dram_init();
660 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
664 sunxi_spl_store_dram_size(gd->ram_size);
667 * Only clock up the CPU to full speed if we are reasonably
668 * assured it's being powered with suitable core voltage
671 clock_set_pll1(get_board_sys_clk());
673 printf("Failed to set core voltage! Can't set CPU frequency\n");
677 #ifdef CONFIG_USB_GADGET
678 int g_dnl_board_usb_cable_connected(void)
684 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
686 pr_err("%s: Cannot find USB device\n", __func__);
690 ret = generic_phy_get_by_name(dev, "usb", &phy);
692 pr_err("failed to get %s USB PHY\n", dev->name);
696 ret = generic_phy_init(&phy);
698 pr_debug("failed to init %s USB PHY\n", dev->name);
702 return sun4i_usb_phy_vbus_detect(&phy);
706 #ifdef CONFIG_SERIAL_TAG
707 void get_board_serial(struct tag_serialnr *serialnr)
710 unsigned long long serial;
712 serial_string = env_get("serial#");
715 serial = simple_strtoull(serial_string, NULL, 16);
717 serialnr->high = (unsigned int) (serial >> 32);
718 serialnr->low = (unsigned int) (serial & 0xffffffff);
727 * Check the SPL header for the "sunxi" variant. If found: parse values
728 * that might have been passed by the loader ("fel" utility), and update
729 * the environment accordingly.
731 static void parse_spl_header(const uint32_t spl_addr)
733 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
735 if (spl == INVALID_SPL_HEADER)
738 if (!spl->fel_script_address)
741 if (spl->fel_uEnv_length != 0) {
743 * data is expected in uEnv.txt compatible format, so "env
744 * import -t" the string(s) at fel_script_address right away.
746 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
747 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
750 /* otherwise assume .scr format (mkimage-type script) */
751 env_set_hex("fel_scriptaddr", spl->fel_script_address);
754 static bool get_unique_sid(unsigned int *sid)
756 if (sunxi_get_sid(sid) != 0)
763 * The single words 1 - 3 of the SID have quite a few bits
764 * which are the same on many models, so we take a crc32
765 * of all 3 words, to get a more unique value.
767 * Note we only do this on newer SoCs as we cannot change
768 * the algorithm on older SoCs since those have been using
769 * fixed mac-addresses based on only using word 3 for a
770 * long time and changing a fixed mac-address with an
771 * u-boot update is not good.
773 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
774 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
775 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
776 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
779 /* Ensure the NIC specific bytes of the mac are not all 0 */
780 if ((sid[3] & 0xffffff) == 0)
787 * Note this function gets called multiple times.
788 * It must not make any changes to env variables which already exist.
790 static void setup_environment(const void *fdt)
792 char serial_string[17] = { 0 };
798 if (!get_unique_sid(sid))
801 for (i = 0; i < 4; i++) {
802 sprintf(ethaddr, "ethernet%d", i);
803 if (!fdt_get_alias(fdt, ethaddr))
807 strcpy(ethaddr, "ethaddr");
809 sprintf(ethaddr, "eth%daddr", i);
811 if (env_get(ethaddr))
814 /* Non OUI / registered MAC address */
815 mac_addr[0] = (i << 4) | 0x02;
816 mac_addr[1] = (sid[0] >> 0) & 0xff;
817 mac_addr[2] = (sid[3] >> 24) & 0xff;
818 mac_addr[3] = (sid[3] >> 16) & 0xff;
819 mac_addr[4] = (sid[3] >> 8) & 0xff;
820 mac_addr[5] = (sid[3] >> 0) & 0xff;
822 eth_env_set_enetaddr(ethaddr, mac_addr);
825 if (!env_get("serial#")) {
826 snprintf(serial_string, sizeof(serial_string),
827 "%08x%08x", sid[0], sid[3]);
829 env_set("serial#", serial_string);
833 int misc_init_r(void)
835 const char *spl_dt_name;
838 env_set("fel_booted", NULL);
839 env_set("fel_scriptaddr", NULL);
840 env_set("mmc_bootdev", NULL);
842 boot = sunxi_get_boot_device();
843 /* determine if we are running in FEL mode */
844 if (boot == BOOT_DEVICE_BOARD) {
845 env_set("fel_booted", "1");
846 parse_spl_header(SPL_ADDR);
847 /* or if we booted from MMC, and which one */
848 } else if (boot == BOOT_DEVICE_MMC1) {
849 env_set("mmc_bootdev", "0");
850 } else if (boot == BOOT_DEVICE_MMC2) {
851 env_set("mmc_bootdev", "1");
854 /* Set fdtfile to match the FIT configuration chosen in SPL. */
855 spl_dt_name = get_spl_dt_name();
857 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
860 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
861 env_set("fdtfile", str);
864 setup_environment(gd->fdt_blob);
869 int board_late_init(void)
871 #ifdef CONFIG_USB_ETHER
878 static void bluetooth_dt_fixup(void *blob)
880 /* Some devices ship with a Bluetooth controller default address.
881 * Set a valid address through the device tree.
883 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
887 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
890 if (eth_env_get_enetaddr("bdaddr", tmp)) {
891 /* Convert between the binary formats of the corresponding stacks */
892 for (i = 0; i < ETH_ALEN; ++i)
893 bdaddr[i] = tmp[ETH_ALEN - i - 1];
895 if (!get_unique_sid(sid))
898 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
899 bdaddr[1] = (sid[3] >> 8) & 0xff;
900 bdaddr[2] = (sid[3] >> 16) & 0xff;
901 bdaddr[3] = (sid[3] >> 24) & 0xff;
902 bdaddr[4] = (sid[0] >> 0) & 0xff;
906 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
907 "local-bd-address", bdaddr, ETH_ALEN, 1);
910 int ft_board_setup(void *blob, struct bd_info *bd)
912 int __maybe_unused r;
915 * Call setup_environment again in case the boot fdt has
916 * ethernet aliases the u-boot copy does not have.
918 setup_environment(blob);
920 bluetooth_dt_fixup(blob);
922 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
923 r = sunxi_simplefb_setup(blob);
930 #ifdef CONFIG_SPL_LOAD_FIT
932 static void set_spl_dt_name(const char *name)
934 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
936 if (spl == INVALID_SPL_HEADER)
939 /* Promote the header version for U-Boot proper, if needed. */
940 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
941 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
943 strcpy((char *)&spl->string_pool, name);
944 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
947 int board_fit_config_name_match(const char *name)
949 const char *best_dt_name = get_spl_dt_name();
952 #ifdef CONFIG_DEFAULT_DEVICE_TREE
953 if (best_dt_name == NULL)
954 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
957 if (best_dt_name == NULL) {
958 /* No DT name was provided, so accept the first config. */
961 #ifdef CONFIG_PINE64_DT_SELECTION
962 if (strstr(best_dt_name, "-pine64-plus")) {
963 /* Differentiate the Pine A64 boards by their DRAM size. */
964 if ((gd->ram_size == 512 * 1024 * 1024))
965 best_dt_name = "sun50i-a64-pine64";
968 #ifdef CONFIG_PINEPHONE_DT_SELECTION
969 if (strstr(best_dt_name, "-pinephone")) {
970 /* Differentiate the PinePhone revisions by GPIO inputs. */
971 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
972 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
973 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
976 /* PL6 is pulled low by the modem on v1.2. */
977 if (gpio_get_value(SUNXI_GPL(6)) == 0)
978 best_dt_name = "sun50i-a64-pinephone-1.2";
980 best_dt_name = "sun50i-a64-pinephone-1.1";
982 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
983 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
984 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
988 ret = strcmp(name, best_dt_name);
991 * If one of the FIT configurations matches the most accurate DT name,
992 * update the SPL header to provide that DT name to U-Boot proper.
995 set_spl_dt_name(best_dt_name);