1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
14 #include <clock_legacy.h>
23 #include <generic-phy.h>
24 #include <phy-sun4i-usb.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/display.h>
28 #include <asm/arch/dram.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/pmic_bus.h>
32 #include <asm/arch/spl.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/global_data.h>
35 #include <linux/delay.h>
36 #include <u-boot/crc.h>
38 #include <asm/armv7.h>
42 #include <u-boot/crc.h>
43 #include <env_internal.h>
44 #include <linux/libfdt.h>
45 #include <fdt_support.h>
50 #include <asm/setup.h>
51 #include <status_led.h>
53 DECLARE_GLOBAL_DATA_PTR;
55 void i2c_init_board(void)
57 #ifdef CONFIG_I2C0_ENABLE
58 #if defined(CONFIG_MACH_SUN4I) || \
59 defined(CONFIG_MACH_SUN5I) || \
60 defined(CONFIG_MACH_SUN7I) || \
61 defined(CONFIG_MACH_SUN8I_R40)
62 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
63 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
64 clock_twi_onoff(0, 1);
65 #elif defined(CONFIG_MACH_SUN6I)
66 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
67 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
68 clock_twi_onoff(0, 1);
69 #elif defined(CONFIG_MACH_SUN8I_V3S)
70 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
71 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
72 clock_twi_onoff(0, 1);
73 #elif defined(CONFIG_MACH_SUN8I)
74 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
75 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
76 clock_twi_onoff(0, 1);
77 #elif defined(CONFIG_MACH_SUN50I)
78 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
79 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
80 clock_twi_onoff(0, 1);
84 #ifdef CONFIG_I2C1_ENABLE
85 #if defined(CONFIG_MACH_SUN4I) || \
86 defined(CONFIG_MACH_SUN7I) || \
87 defined(CONFIG_MACH_SUN8I_R40)
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
90 clock_twi_onoff(1, 1);
91 #elif defined(CONFIG_MACH_SUN5I)
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
94 clock_twi_onoff(1, 1);
95 #elif defined(CONFIG_MACH_SUN6I)
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
98 clock_twi_onoff(1, 1);
99 #elif defined(CONFIG_MACH_SUN8I)
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
102 clock_twi_onoff(1, 1);
103 #elif defined(CONFIG_MACH_SUN50I)
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
106 clock_twi_onoff(1, 1);
110 #ifdef CONFIG_R_I2C_ENABLE
111 #ifdef CONFIG_MACH_SUN50I
112 clock_twi_onoff(5, 1);
113 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
114 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
115 #elif CONFIG_MACH_SUN50I_H616
116 clock_twi_onoff(5, 1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
118 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
120 clock_twi_onoff(5, 1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
122 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
128 * Try to use the environment from the boot source first.
129 * For MMC, this means a FAT partition on the boot device (SD or eMMC).
130 * If the raw MMC environment is also enabled, this is tried next.
131 * When booting from NAND we try UBI first, then NAND directly.
132 * SPI flash falls back to FAT (on SD card).
134 enum env_location env_get_location(enum env_operation op, int prio)
139 /* NOWHERE is exclusive, no other option can be defined. */
140 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
143 switch (sunxi_get_boot_device()) {
144 case BOOT_DEVICE_MMC1:
145 case BOOT_DEVICE_MMC2:
146 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
148 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
151 case BOOT_DEVICE_NAND:
152 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
154 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
157 case BOOT_DEVICE_SPI:
158 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
159 return ENVL_SPI_FLASH;
160 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
163 case BOOT_DEVICE_BOARD:
170 * If we come here for the first time, we *must* return a valid
171 * environment location other than ENVL_UNKNOWN, or the setup sequence
172 * in board_f() will silently hang. This is arguably a bug in
173 * env_init(), but for now pick one environment for which we know for
174 * sure to have a driver for. For all defconfigs this is either FAT
175 * or UBI, or NOWHERE, which is already handled above.
178 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
180 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
187 /* add board specific code here */
190 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
192 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
194 #if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
195 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
196 debug("id_pfr1: 0x%08x\n", id_pfr1);
197 /* Generic Timer Extension available? */
198 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
201 debug("Setting CNTFRQ\n");
204 * CNTFRQ is a secure register, so we will crash if we try to
205 * write this from the non-secure world (read is OK, though).
206 * In case some bootcode has already set the correct value,
207 * we avoid the risk of writing to it.
209 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
210 if (freq != CONFIG_COUNTER_FREQUENCY) {
211 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
212 freq, CONFIG_COUNTER_FREQUENCY);
213 #ifdef CONFIG_NON_SECURE
214 printf("arch timer frequency is wrong, but cannot adjust it\n");
216 asm volatile("mcr p15, 0, %0, c14, c0, 0"
217 : : "r"(CONFIG_COUNTER_FREQUENCY));
221 #endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
223 ret = axp_gpio_init();
227 /* strcmp() would look better, but doesn't get optimised away. */
228 if (CONFIG_SATAPWR[0]) {
229 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
230 if (satapwr_pin >= 0) {
231 gpio_request(satapwr_pin, "satapwr");
232 gpio_direction_output(satapwr_pin, 1);
235 * Give the attached SATA device time to power-up
236 * to avoid link timeouts
242 if (CONFIG_MACPWR[0]) {
243 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
244 if (macpwr_pin >= 0) {
245 gpio_request(macpwr_pin, "macpwr");
246 gpio_direction_output(macpwr_pin, 1);
250 #if CONFIG_IS_ENABLED(DM_I2C)
252 * Temporary workaround for enabling I2C clocks until proper sunxi DM
253 * clk, reset and pinctrl drivers land.
264 * On older SoCs the SPL is actually at address zero, so using NULL as
265 * an error value does not work.
267 #define INVALID_SPL_HEADER ((void *)~0UL)
269 static struct boot_file_head * get_spl_header(uint8_t req_version)
271 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
272 uint8_t spl_header_version = spl->spl_signature[3];
274 /* Is there really the SPL header (still) there? */
275 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
276 return INVALID_SPL_HEADER;
278 if (spl_header_version < req_version) {
279 printf("sunxi SPL version mismatch: expected %u, got %u\n",
280 req_version, spl_header_version);
281 return INVALID_SPL_HEADER;
287 static const char *get_spl_dt_name(void)
289 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
291 /* Check if there is a DT name stored in the SPL header. */
292 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
293 return (char *)spl + spl->dt_name_offset;
300 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
302 if (spl == INVALID_SPL_HEADER)
303 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
306 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
308 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
309 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
314 #if defined(CONFIG_NAND_SUNXI)
315 static void nand_pinmux_setup(void)
319 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
320 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
322 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
323 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
324 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
326 /* sun4i / sun7i do have a PC23, but it is not used for nand,
327 * only sun7i has a PC24 */
328 #ifdef CONFIG_MACH_SUN7I
329 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
333 static void nand_clock_setup(void)
335 struct sunxi_ccm_reg *const ccm =
336 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
338 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
339 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
340 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
341 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
343 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
346 void board_nand_init(void)
350 #ifndef CONFIG_SPL_BUILD
354 #endif /* CONFIG_NAND_SUNXI */
357 static void mmc_pinmux_setup(int sdc)
364 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
365 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
366 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
367 sunxi_gpio_set_drv(pin, 2);
372 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
373 defined(CONFIG_MACH_SUN8I_R40)
374 if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
375 /* SDC1: PH22-PH-27 */
376 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
377 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
378 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
379 sunxi_gpio_set_drv(pin, 2);
383 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
384 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
385 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
386 sunxi_gpio_set_drv(pin, 2);
389 #elif defined(CONFIG_MACH_SUN5I)
391 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
392 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
393 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
394 sunxi_gpio_set_drv(pin, 2);
396 #elif defined(CONFIG_MACH_SUN6I)
398 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
399 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
400 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
401 sunxi_gpio_set_drv(pin, 2);
403 #elif defined(CONFIG_MACH_SUN8I)
405 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
406 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
407 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
408 sunxi_gpio_set_drv(pin, 2);
414 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
416 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
417 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
418 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
419 sunxi_gpio_set_drv(pin, 2);
421 #elif defined(CONFIG_MACH_SUN5I)
423 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
424 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
425 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
426 sunxi_gpio_set_drv(pin, 2);
428 #elif defined(CONFIG_MACH_SUN6I)
429 /* SDC2: PC6-PC15, PC24 */
430 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
431 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
432 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
433 sunxi_gpio_set_drv(pin, 2);
436 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
437 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
438 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
439 #elif defined(CONFIG_MACH_SUN8I_R40)
440 /* SDC2: PC6-PC15, PC24 */
441 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
442 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
443 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
444 sunxi_gpio_set_drv(pin, 2);
447 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
448 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
449 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
450 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
451 /* SDC2: PC5-PC6, PC8-PC16 */
452 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
453 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
454 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
455 sunxi_gpio_set_drv(pin, 2);
458 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
459 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
460 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
461 sunxi_gpio_set_drv(pin, 2);
463 #elif defined(CONFIG_MACH_SUN50I_H6)
465 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
466 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
467 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
468 sunxi_gpio_set_drv(pin, 2);
470 #elif defined(CONFIG_MACH_SUN50I_H616)
471 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
472 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
473 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
475 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
477 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
478 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
479 sunxi_gpio_set_drv(pin, 3);
481 #elif defined(CONFIG_MACH_SUN9I)
483 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
484 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
485 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
486 sunxi_gpio_set_drv(pin, 2);
489 puts("ERROR: No pinmux setup defined for MMC2!\n");
494 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
495 defined(CONFIG_MACH_SUN8I_R40)
497 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
498 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
499 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
500 sunxi_gpio_set_drv(pin, 2);
502 #elif defined(CONFIG_MACH_SUN6I)
503 /* SDC3: PC6-PC15, PC24 */
504 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
505 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
506 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
507 sunxi_gpio_set_drv(pin, 2);
510 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
511 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
512 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
517 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
522 int board_mmc_init(struct bd_info *bis)
525 * The BROM always accesses MMC port 0 (typically an SD card), and
526 * most boards seem to have such a slot. The others haven't reported
527 * any problem with unconditionally enabling this in the SPL.
529 if (!IS_ENABLED(CONFIG_UART0_PORT_F)) {
531 if (!sunxi_mmc_init(0))
535 if (CONFIG_MMC_SUNXI_SLOT_EXTRA != -1) {
536 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
537 if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA))
544 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
545 int mmc_get_env_dev(void)
547 switch (sunxi_get_boot_device()) {
548 case BOOT_DEVICE_MMC1:
550 case BOOT_DEVICE_MMC2:
553 return CONFIG_SYS_MMC_ENV_DEV;
557 #endif /* CONFIG_MMC */
559 #ifdef CONFIG_SPL_BUILD
561 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
563 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
565 if (spl == INVALID_SPL_HEADER)
568 /* Promote the header version for U-Boot proper, if needed. */
569 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
570 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
572 spl->dram_size = dram_size >> 20;
575 void sunxi_board_init(void)
577 int power_failed = 0;
579 #ifdef CONFIG_LED_STATUS
580 if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
584 #ifdef CONFIG_SY8106A_POWER
585 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
588 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
589 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
590 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
591 power_failed = axp_init();
593 if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
596 pmic_bus_read(AXP_POWER_STATUS, &boot_reason);
597 if (boot_reason & AXP_POWER_STATUS_ALDO_IN) {
598 printf("Power on by plug-in, shutting down.\n");
599 pmic_bus_write(0x32, BIT(7));
603 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
604 defined CONFIG_AXP818_POWER
605 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
607 #if !defined(CONFIG_AXP305_POWER)
608 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
609 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
611 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
612 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
614 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
615 defined CONFIG_AXP818_POWER
616 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
619 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
620 defined CONFIG_AXP818_POWER
621 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
623 #if !defined(CONFIG_AXP305_POWER)
624 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
626 #if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
627 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
629 #ifdef CONFIG_AXP209_POWER
630 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
633 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
634 defined(CONFIG_AXP818_POWER)
635 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
636 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
637 #if !defined CONFIG_AXP809_POWER
638 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
639 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
641 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
642 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
643 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
646 #ifdef CONFIG_AXP818_POWER
647 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
648 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
649 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
652 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
653 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
657 gd->ram_size = sunxi_dram_init();
658 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
662 sunxi_spl_store_dram_size(gd->ram_size);
665 * Only clock up the CPU to full speed if we are reasonably
666 * assured it's being powered with suitable core voltage
669 clock_set_pll1(get_board_sys_clk());
671 printf("Failed to set core voltage! Can't set CPU frequency\n");
673 #endif /* CONFIG_SPL_BUILD */
675 #ifdef CONFIG_USB_GADGET
676 int g_dnl_board_usb_cable_connected(void)
682 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
684 pr_err("%s: Cannot find USB device\n", __func__);
688 ret = generic_phy_get_by_name(dev, "usb", &phy);
690 pr_err("failed to get %s USB PHY\n", dev->name);
694 ret = generic_phy_init(&phy);
696 pr_debug("failed to init %s USB PHY\n", dev->name);
700 return sun4i_usb_phy_vbus_detect(&phy);
702 #endif /* CONFIG_USB_GADGET */
704 #ifdef CONFIG_SERIAL_TAG
705 void get_board_serial(struct tag_serialnr *serialnr)
708 unsigned long long serial;
710 serial_string = env_get("serial#");
713 serial = simple_strtoull(serial_string, NULL, 16);
715 serialnr->high = (unsigned int) (serial >> 32);
716 serialnr->low = (unsigned int) (serial & 0xffffffff);
725 * Check the SPL header for the "sunxi" variant. If found: parse values
726 * that might have been passed by the loader ("fel" utility), and update
727 * the environment accordingly.
729 static void parse_spl_header(const uint32_t spl_addr)
731 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
733 if (spl == INVALID_SPL_HEADER)
736 if (!spl->fel_script_address)
739 if (spl->fel_uEnv_length != 0) {
741 * data is expected in uEnv.txt compatible format, so "env
742 * import -t" the string(s) at fel_script_address right away.
744 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
745 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
748 /* otherwise assume .scr format (mkimage-type script) */
749 env_set_hex("fel_scriptaddr", spl->fel_script_address);
752 static bool get_unique_sid(unsigned int *sid)
754 if (sunxi_get_sid(sid) != 0)
761 * The single words 1 - 3 of the SID have quite a few bits
762 * which are the same on many models, so we take a crc32
763 * of all 3 words, to get a more unique value.
765 * Note we only do this on newer SoCs as we cannot change
766 * the algorithm on older SoCs since those have been using
767 * fixed mac-addresses based on only using word 3 for a
768 * long time and changing a fixed mac-address with an
769 * u-boot update is not good.
771 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
772 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
773 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
774 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
777 /* Ensure the NIC specific bytes of the mac are not all 0 */
778 if ((sid[3] & 0xffffff) == 0)
785 * Note this function gets called multiple times.
786 * It must not make any changes to env variables which already exist.
788 static void setup_environment(const void *fdt)
790 char serial_string[17] = { 0 };
796 if (!get_unique_sid(sid))
799 for (i = 0; i < 4; i++) {
800 sprintf(ethaddr, "ethernet%d", i);
801 if (!fdt_get_alias(fdt, ethaddr))
805 strcpy(ethaddr, "ethaddr");
807 sprintf(ethaddr, "eth%daddr", i);
809 if (env_get(ethaddr))
812 /* Non OUI / registered MAC address */
813 mac_addr[0] = (i << 4) | 0x02;
814 mac_addr[1] = (sid[0] >> 0) & 0xff;
815 mac_addr[2] = (sid[3] >> 24) & 0xff;
816 mac_addr[3] = (sid[3] >> 16) & 0xff;
817 mac_addr[4] = (sid[3] >> 8) & 0xff;
818 mac_addr[5] = (sid[3] >> 0) & 0xff;
820 eth_env_set_enetaddr(ethaddr, mac_addr);
823 if (!env_get("serial#")) {
824 snprintf(serial_string, sizeof(serial_string),
825 "%08x%08x", sid[0], sid[3]);
827 env_set("serial#", serial_string);
831 int misc_init_r(void)
833 const char *spl_dt_name;
836 env_set("fel_booted", NULL);
837 env_set("fel_scriptaddr", NULL);
838 env_set("mmc_bootdev", NULL);
840 boot = sunxi_get_boot_device();
841 /* determine if we are running in FEL mode */
842 if (boot == BOOT_DEVICE_BOARD) {
843 env_set("fel_booted", "1");
844 parse_spl_header(SPL_ADDR);
845 /* or if we booted from MMC, and which one */
846 } else if (boot == BOOT_DEVICE_MMC1) {
847 env_set("mmc_bootdev", "0");
848 } else if (boot == BOOT_DEVICE_MMC2) {
849 env_set("mmc_bootdev", "1");
852 /* Set fdtfile to match the FIT configuration chosen in SPL. */
853 spl_dt_name = get_spl_dt_name();
855 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
858 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
859 env_set("fdtfile", str);
862 setup_environment(gd->fdt_blob);
867 int board_late_init(void)
869 #ifdef CONFIG_USB_ETHER
876 static void bluetooth_dt_fixup(void *blob)
878 /* Some devices ship with a Bluetooth controller default address.
879 * Set a valid address through the device tree.
881 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
885 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
888 if (eth_env_get_enetaddr("bdaddr", tmp)) {
889 /* Convert between the binary formats of the corresponding stacks */
890 for (i = 0; i < ETH_ALEN; ++i)
891 bdaddr[i] = tmp[ETH_ALEN - i - 1];
893 if (!get_unique_sid(sid))
896 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
897 bdaddr[1] = (sid[3] >> 8) & 0xff;
898 bdaddr[2] = (sid[3] >> 16) & 0xff;
899 bdaddr[3] = (sid[3] >> 24) & 0xff;
900 bdaddr[4] = (sid[0] >> 0) & 0xff;
904 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
905 "local-bd-address", bdaddr, ETH_ALEN, 1);
908 int ft_board_setup(void *blob, struct bd_info *bd)
910 int __maybe_unused r;
913 * Call setup_environment and fdt_fixup_ethernet again
914 * in case the boot fdt has ethernet aliases the u-boot
915 * copy does not have.
917 setup_environment(blob);
918 fdt_fixup_ethernet(blob);
920 bluetooth_dt_fixup(blob);
922 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
923 r = sunxi_simplefb_setup(blob);
930 #ifdef CONFIG_SPL_LOAD_FIT
931 static void set_spl_dt_name(const char *name)
933 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
935 if (spl == INVALID_SPL_HEADER)
938 /* Promote the header version for U-Boot proper, if needed. */
939 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
940 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
942 strcpy((char *)&spl->string_pool, name);
943 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
946 int board_fit_config_name_match(const char *name)
948 const char *best_dt_name = get_spl_dt_name();
951 #ifdef CONFIG_DEFAULT_DEVICE_TREE
952 if (best_dt_name == NULL)
953 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
956 if (best_dt_name == NULL) {
957 /* No DT name was provided, so accept the first config. */
960 #ifdef CONFIG_PINE64_DT_SELECTION
961 if (strstr(best_dt_name, "-pine64-plus")) {
962 /* Differentiate the Pine A64 boards by their DRAM size. */
963 if ((gd->ram_size == 512 * 1024 * 1024))
964 best_dt_name = "sun50i-a64-pine64";
967 #ifdef CONFIG_PINEPHONE_DT_SELECTION
968 if (strstr(best_dt_name, "-pinephone")) {
969 /* Differentiate the PinePhone revisions by GPIO inputs. */
970 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
971 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
972 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
975 /* PL6 is pulled low by the modem on v1.2. */
976 if (gpio_get_value(SUNXI_GPL(6)) == 0)
977 best_dt_name = "sun50i-a64-pinephone-1.2";
979 best_dt_name = "sun50i-a64-pinephone-1.1";
981 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
982 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
983 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
987 ret = strcmp(name, best_dt_name);
990 * If one of the FIT configurations matches the most accurate DT name,
991 * update the SPL header to provide that DT name to U-Boot proper.
994 set_spl_dt_name(best_dt_name);
998 #endif /* CONFIG_SPL_LOAD_FIT */