1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
22 #include <generic-phy.h>
23 #include <phy-sun4i-usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/display.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/spl.h>
32 #include <linux/delay.h>
33 #include <u-boot/crc.h>
35 #include <asm/armv7.h>
39 #include <u-boot/crc.h>
40 #include <env_internal.h>
41 #include <linux/libfdt.h>
46 #include <asm/setup.h>
48 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
49 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
50 int soft_i2c_gpio_sda;
51 int soft_i2c_gpio_scl;
53 static int soft_i2c_board_init(void)
57 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
58 if (soft_i2c_gpio_sda < 0) {
59 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
60 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
61 return soft_i2c_gpio_sda;
63 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
65 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
66 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
70 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
71 if (soft_i2c_gpio_scl < 0) {
72 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
73 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
74 return soft_i2c_gpio_scl;
76 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
78 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
79 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
86 static int soft_i2c_board_init(void) { return 0; }
89 DECLARE_GLOBAL_DATA_PTR;
91 void i2c_init_board(void)
93 #ifdef CONFIG_I2C0_ENABLE
94 #if defined(CONFIG_MACH_SUN4I) || \
95 defined(CONFIG_MACH_SUN5I) || \
96 defined(CONFIG_MACH_SUN7I) || \
97 defined(CONFIG_MACH_SUN8I_R40)
98 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
100 clock_twi_onoff(0, 1);
101 #elif defined(CONFIG_MACH_SUN6I)
102 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
104 clock_twi_onoff(0, 1);
105 #elif defined(CONFIG_MACH_SUN8I_V3S)
106 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
107 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
108 clock_twi_onoff(0, 1);
109 #elif defined(CONFIG_MACH_SUN8I)
110 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
111 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
112 clock_twi_onoff(0, 1);
113 #elif defined(CONFIG_MACH_SUN50I)
114 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
115 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
116 clock_twi_onoff(0, 1);
120 #ifdef CONFIG_I2C1_ENABLE
121 #if defined(CONFIG_MACH_SUN4I) || \
122 defined(CONFIG_MACH_SUN7I) || \
123 defined(CONFIG_MACH_SUN8I_R40)
124 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
125 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
126 clock_twi_onoff(1, 1);
127 #elif defined(CONFIG_MACH_SUN5I)
128 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
130 clock_twi_onoff(1, 1);
131 #elif defined(CONFIG_MACH_SUN6I)
132 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
134 clock_twi_onoff(1, 1);
135 #elif defined(CONFIG_MACH_SUN8I)
136 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
137 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
138 clock_twi_onoff(1, 1);
139 #elif defined(CONFIG_MACH_SUN50I)
140 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
141 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
142 clock_twi_onoff(1, 1);
146 #ifdef CONFIG_I2C2_ENABLE
147 #if defined(CONFIG_MACH_SUN4I) || \
148 defined(CONFIG_MACH_SUN7I) || \
149 defined(CONFIG_MACH_SUN8I_R40)
150 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
151 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
152 clock_twi_onoff(2, 1);
153 #elif defined(CONFIG_MACH_SUN5I)
154 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
155 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
156 clock_twi_onoff(2, 1);
157 #elif defined(CONFIG_MACH_SUN6I)
158 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
159 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
160 clock_twi_onoff(2, 1);
161 #elif defined(CONFIG_MACH_SUN8I)
162 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
163 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
164 clock_twi_onoff(2, 1);
165 #elif defined(CONFIG_MACH_SUN50I)
166 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
167 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
168 clock_twi_onoff(2, 1);
172 #ifdef CONFIG_I2C3_ENABLE
173 #if defined(CONFIG_MACH_SUN6I)
174 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
175 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
176 clock_twi_onoff(3, 1);
177 #elif defined(CONFIG_MACH_SUN7I) || \
178 defined(CONFIG_MACH_SUN8I_R40)
179 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
180 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
181 clock_twi_onoff(3, 1);
185 #ifdef CONFIG_I2C4_ENABLE
186 #if defined(CONFIG_MACH_SUN7I) || \
187 defined(CONFIG_MACH_SUN8I_R40)
188 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
189 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
190 clock_twi_onoff(4, 1);
194 #ifdef CONFIG_R_I2C_ENABLE
195 #ifdef CONFIG_MACH_SUN50I
196 clock_twi_onoff(5, 1);
197 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
198 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
200 clock_twi_onoff(5, 1);
201 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
202 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
207 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
208 enum env_location env_get_location(enum env_operation op, int prio)
224 static void mmc_pinmux_setup(int sdc);
227 /* add board specific code here */
230 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
232 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
235 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
236 debug("id_pfr1: 0x%08x\n", id_pfr1);
237 /* Generic Timer Extension available? */
238 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
241 debug("Setting CNTFRQ\n");
244 * CNTFRQ is a secure register, so we will crash if we try to
245 * write this from the non-secure world (read is OK, though).
246 * In case some bootcode has already set the correct value,
247 * we avoid the risk of writing to it.
249 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
250 if (freq != COUNTER_FREQUENCY) {
251 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
252 freq, COUNTER_FREQUENCY);
253 #ifdef CONFIG_NON_SECURE
254 printf("arch timer frequency is wrong, but cannot adjust it\n");
256 asm volatile("mcr p15, 0, %0, c14, c0, 0"
257 : : "r"(COUNTER_FREQUENCY));
261 #endif /* !CONFIG_ARM64 */
263 ret = axp_gpio_init();
267 #ifdef CONFIG_SATAPWR
268 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
269 gpio_request(satapwr_pin, "satapwr");
270 gpio_direction_output(satapwr_pin, 1);
271 /* Give attached sata device time to power-up to avoid link timeouts */
275 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
276 gpio_request(macpwr_pin, "macpwr");
277 gpio_direction_output(macpwr_pin, 1);
282 * Temporary workaround for enabling I2C clocks until proper sunxi DM
283 * clk, reset and pinctrl drivers land.
290 * Temporary workaround for enabling MMC clocks until a sunxi DM
291 * pinctrl driver lands.
293 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
294 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
295 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
297 #endif /* CONFIG_DM_MMC */
299 /* Uses dm gpio code so do this here and not in i2c_init_board() */
300 return soft_i2c_board_init();
304 * On older SoCs the SPL is actually at address zero, so using NULL as
305 * an error value does not work.
307 #define INVALID_SPL_HEADER ((void *)~0UL)
309 static struct boot_file_head * get_spl_header(uint8_t req_version)
311 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
312 uint8_t spl_header_version = spl->spl_signature[3];
314 /* Is there really the SPL header (still) there? */
315 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
316 return INVALID_SPL_HEADER;
318 if (spl_header_version < req_version) {
319 printf("sunxi SPL version mismatch: expected %u, got %u\n",
320 req_version, spl_header_version);
321 return INVALID_SPL_HEADER;
327 static const char *get_spl_dt_name(void)
329 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
331 /* Check if there is a DT name stored in the SPL header. */
332 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
333 return (char *)spl + spl->dt_name_offset;
340 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
342 if (spl == INVALID_SPL_HEADER)
343 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
346 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
348 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
349 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
354 #if defined(CONFIG_NAND_SUNXI)
355 static void nand_pinmux_setup(void)
359 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
360 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
362 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
363 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
364 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
366 /* sun4i / sun7i do have a PC23, but it is not used for nand,
367 * only sun7i has a PC24 */
368 #ifdef CONFIG_MACH_SUN7I
369 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
373 static void nand_clock_setup(void)
375 struct sunxi_ccm_reg *const ccm =
376 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
378 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
379 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
380 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
381 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
383 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
386 void board_nand_init(void)
390 #ifndef CONFIG_SPL_BUILD
397 static void mmc_pinmux_setup(int sdc)
400 __maybe_unused int pins;
405 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
406 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
407 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
408 sunxi_gpio_set_drv(pin, 2);
413 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
415 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
416 defined(CONFIG_MACH_SUN8I_R40)
417 if (pins == SUNXI_GPIO_H) {
418 /* SDC1: PH22-PH-27 */
419 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
420 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
421 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
422 sunxi_gpio_set_drv(pin, 2);
426 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
427 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
428 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
429 sunxi_gpio_set_drv(pin, 2);
432 #elif defined(CONFIG_MACH_SUN5I)
434 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
435 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
436 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
437 sunxi_gpio_set_drv(pin, 2);
439 #elif defined(CONFIG_MACH_SUN6I)
441 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
442 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
443 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
444 sunxi_gpio_set_drv(pin, 2);
446 #elif defined(CONFIG_MACH_SUN8I)
447 if (pins == SUNXI_GPIO_D) {
449 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
450 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
451 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
452 sunxi_gpio_set_drv(pin, 2);
456 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
457 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
458 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
459 sunxi_gpio_set_drv(pin, 2);
466 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
468 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
470 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
471 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
472 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
473 sunxi_gpio_set_drv(pin, 2);
475 #elif defined(CONFIG_MACH_SUN5I)
476 if (pins == SUNXI_GPIO_E) {
478 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
479 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
480 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
481 sunxi_gpio_set_drv(pin, 2);
485 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
486 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
487 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
488 sunxi_gpio_set_drv(pin, 2);
491 #elif defined(CONFIG_MACH_SUN6I)
492 if (pins == SUNXI_GPIO_A) {
494 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
495 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
496 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
497 sunxi_gpio_set_drv(pin, 2);
500 /* SDC2: PC6-PC15, PC24 */
501 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
502 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
503 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
504 sunxi_gpio_set_drv(pin, 2);
507 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
508 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
509 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
511 #elif defined(CONFIG_MACH_SUN8I_R40)
512 /* SDC2: PC6-PC15, PC24 */
513 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
514 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
515 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
516 sunxi_gpio_set_drv(pin, 2);
519 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
520 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
521 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
522 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
523 /* SDC2: PC5-PC6, PC8-PC16 */
524 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
525 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
526 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
527 sunxi_gpio_set_drv(pin, 2);
530 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
531 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
532 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
533 sunxi_gpio_set_drv(pin, 2);
535 #elif defined(CONFIG_MACH_SUN50I_H6)
537 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
538 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
539 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
540 sunxi_gpio_set_drv(pin, 2);
542 #elif defined(CONFIG_MACH_SUN9I)
544 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
545 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
546 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
547 sunxi_gpio_set_drv(pin, 2);
553 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
555 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
556 defined(CONFIG_MACH_SUN8I_R40)
558 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
559 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
560 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
561 sunxi_gpio_set_drv(pin, 2);
563 #elif defined(CONFIG_MACH_SUN6I)
564 if (pins == SUNXI_GPIO_A) {
566 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
567 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
568 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
569 sunxi_gpio_set_drv(pin, 2);
572 /* SDC3: PC6-PC15, PC24 */
573 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
574 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
575 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
576 sunxi_gpio_set_drv(pin, 2);
579 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
580 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
581 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
587 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
592 int board_mmc_init(struct bd_info *bis)
594 __maybe_unused struct mmc *mmc0, *mmc1;
596 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
597 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
601 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
602 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
603 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
612 #ifdef CONFIG_SPL_BUILD
614 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
616 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
618 if (spl == INVALID_SPL_HEADER)
621 /* Promote the header version for U-Boot proper, if needed. */
622 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
623 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
625 spl->dram_size = dram_size >> 20;
628 void sunxi_board_init(void)
630 int power_failed = 0;
632 #ifdef CONFIG_SY8106A_POWER
633 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
636 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
637 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
638 defined CONFIG_AXP818_POWER
639 power_failed = axp_init();
641 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
642 defined CONFIG_AXP818_POWER
643 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
645 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
646 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
647 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
648 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
650 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
651 defined CONFIG_AXP818_POWER
652 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
655 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
656 defined CONFIG_AXP818_POWER
657 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
659 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
660 #if !defined(CONFIG_AXP152_POWER)
661 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
663 #ifdef CONFIG_AXP209_POWER
664 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
667 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
668 defined(CONFIG_AXP818_POWER)
669 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
670 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
671 #if !defined CONFIG_AXP809_POWER
672 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
673 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
675 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
676 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
677 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
680 #ifdef CONFIG_AXP818_POWER
681 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
682 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
683 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
686 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
687 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
691 gd->ram_size = sunxi_dram_init();
692 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
696 sunxi_spl_store_dram_size(gd->ram_size);
699 * Only clock up the CPU to full speed if we are reasonably
700 * assured it's being powered with suitable core voltage
703 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
705 printf("Failed to set core voltage! Can't set CPU frequency\n");
709 #ifdef CONFIG_USB_GADGET
710 int g_dnl_board_usb_cable_connected(void)
716 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
718 pr_err("%s: Cannot find USB device\n", __func__);
722 ret = generic_phy_get_by_name(dev, "usb", &phy);
724 pr_err("failed to get %s USB PHY\n", dev->name);
728 ret = generic_phy_init(&phy);
730 pr_debug("failed to init %s USB PHY\n", dev->name);
734 ret = sun4i_usb_phy_vbus_detect(&phy);
736 pr_err("A charger is plugged into the OTG\n");
744 #ifdef CONFIG_SERIAL_TAG
745 void get_board_serial(struct tag_serialnr *serialnr)
748 unsigned long long serial;
750 serial_string = env_get("serial#");
753 serial = simple_strtoull(serial_string, NULL, 16);
755 serialnr->high = (unsigned int) (serial >> 32);
756 serialnr->low = (unsigned int) (serial & 0xffffffff);
765 * Check the SPL header for the "sunxi" variant. If found: parse values
766 * that might have been passed by the loader ("fel" utility), and update
767 * the environment accordingly.
769 static void parse_spl_header(const uint32_t spl_addr)
771 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
773 if (spl == INVALID_SPL_HEADER)
776 if (!spl->fel_script_address)
779 if (spl->fel_uEnv_length != 0) {
781 * data is expected in uEnv.txt compatible format, so "env
782 * import -t" the string(s) at fel_script_address right away.
784 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
785 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
788 /* otherwise assume .scr format (mkimage-type script) */
789 env_set_hex("fel_scriptaddr", spl->fel_script_address);
793 * Note this function gets called multiple times.
794 * It must not make any changes to env variables which already exist.
796 static void setup_environment(const void *fdt)
798 char serial_string[17] = { 0 };
804 ret = sunxi_get_sid(sid);
805 if (ret == 0 && sid[0] != 0) {
807 * The single words 1 - 3 of the SID have quite a few bits
808 * which are the same on many models, so we take a crc32
809 * of all 3 words, to get a more unique value.
811 * Note we only do this on newer SoCs as we cannot change
812 * the algorithm on older SoCs since those have been using
813 * fixed mac-addresses based on only using word 3 for a
814 * long time and changing a fixed mac-address with an
815 * u-boot update is not good.
817 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
818 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
819 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
820 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
823 /* Ensure the NIC specific bytes of the mac are not all 0 */
824 if ((sid[3] & 0xffffff) == 0)
827 for (i = 0; i < 4; i++) {
828 sprintf(ethaddr, "ethernet%d", i);
829 if (!fdt_get_alias(fdt, ethaddr))
833 strcpy(ethaddr, "ethaddr");
835 sprintf(ethaddr, "eth%daddr", i);
837 if (env_get(ethaddr))
840 /* Non OUI / registered MAC address */
841 mac_addr[0] = (i << 4) | 0x02;
842 mac_addr[1] = (sid[0] >> 0) & 0xff;
843 mac_addr[2] = (sid[3] >> 24) & 0xff;
844 mac_addr[3] = (sid[3] >> 16) & 0xff;
845 mac_addr[4] = (sid[3] >> 8) & 0xff;
846 mac_addr[5] = (sid[3] >> 0) & 0xff;
848 eth_env_set_enetaddr(ethaddr, mac_addr);
851 if (!env_get("serial#")) {
852 snprintf(serial_string, sizeof(serial_string),
853 "%08x%08x", sid[0], sid[3]);
855 env_set("serial#", serial_string);
860 int misc_init_r(void)
862 const char *spl_dt_name;
865 env_set("fel_booted", NULL);
866 env_set("fel_scriptaddr", NULL);
867 env_set("mmc_bootdev", NULL);
869 boot = sunxi_get_boot_device();
870 /* determine if we are running in FEL mode */
871 if (boot == BOOT_DEVICE_BOARD) {
872 env_set("fel_booted", "1");
873 parse_spl_header(SPL_ADDR);
874 /* or if we booted from MMC, and which one */
875 } else if (boot == BOOT_DEVICE_MMC1) {
876 env_set("mmc_bootdev", "0");
877 } else if (boot == BOOT_DEVICE_MMC2) {
878 env_set("mmc_bootdev", "1");
881 /* Set fdtfile to match the FIT configuration chosen in SPL. */
882 spl_dt_name = get_spl_dt_name();
884 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
887 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
888 env_set("fdtfile", str);
891 setup_environment(gd->fdt_blob);
893 #ifdef CONFIG_USB_ETHER
900 int ft_board_setup(void *blob, struct bd_info *bd)
902 int __maybe_unused r;
905 * Call setup_environment again in case the boot fdt has
906 * ethernet aliases the u-boot copy does not have.
908 setup_environment(blob);
910 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
911 r = sunxi_simplefb_setup(blob);
918 #ifdef CONFIG_SPL_LOAD_FIT
920 static void set_spl_dt_name(const char *name)
922 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
924 if (spl == INVALID_SPL_HEADER)
927 /* Promote the header version for U-Boot proper, if needed. */
928 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
929 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
931 strcpy((char *)&spl->string_pool, name);
932 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
935 int board_fit_config_name_match(const char *name)
937 const char *best_dt_name = get_spl_dt_name();
940 #ifdef CONFIG_DEFAULT_DEVICE_TREE
941 if (best_dt_name == NULL)
942 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
945 if (best_dt_name == NULL) {
946 /* No DT name was provided, so accept the first config. */
949 #ifdef CONFIG_PINE64_DT_SELECTION
950 if (strstr(best_dt_name, "-pine64-plus")) {
951 /* Differentiate the Pine A64 boards by their DRAM size. */
952 if ((gd->ram_size == 512 * 1024 * 1024))
953 best_dt_name = "sun50i-a64-pine64";
956 #ifdef CONFIG_PINEPHONE_DT_SELECTION
957 if (strstr(best_dt_name, "-pinephone")) {
958 /* Differentiate the PinePhone revisions by GPIO inputs. */
959 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
960 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
961 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
964 /* PL6 is pulled low by the modem on v1.2. */
965 if (gpio_get_value(SUNXI_GPL(6)) == 0)
966 best_dt_name = "sun50i-a64-pinephone-1.2";
968 best_dt_name = "sun50i-a64-pinephone-1.1";
970 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
971 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
972 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
976 ret = strcmp(name, best_dt_name);
979 * If one of the FIT configurations matches the most accurate DT name,
980 * update the SPL header to provide that DT name to U-Boot proper.
983 set_spl_dt_name(best_dt_name);