1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
14 #include <clock_legacy.h>
23 #include <generic-phy.h>
24 #include <phy-sun4i-usb.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/display.h>
28 #include <asm/arch/dram.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/pmic_bus.h>
32 #include <asm/arch/spl.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/global_data.h>
35 #include <linux/delay.h>
36 #include <u-boot/crc.h>
38 #include <asm/armv7.h>
42 #include <u-boot/crc.h>
43 #include <env_internal.h>
44 #include <linux/libfdt.h>
45 #include <fdt_support.h>
50 #include <asm/setup.h>
51 #include <status_led.h>
53 DECLARE_GLOBAL_DATA_PTR;
55 void i2c_init_board(void)
57 #ifdef CONFIG_I2C0_ENABLE
58 #if defined(CONFIG_MACH_SUN4I) || \
59 defined(CONFIG_MACH_SUN5I) || \
60 defined(CONFIG_MACH_SUN7I) || \
61 defined(CONFIG_MACH_SUN8I_R40)
62 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
63 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
64 clock_twi_onoff(0, 1);
65 #elif defined(CONFIG_MACH_SUN6I)
66 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
67 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
68 clock_twi_onoff(0, 1);
69 #elif defined(CONFIG_MACH_SUN8I_V3S)
70 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
71 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
72 clock_twi_onoff(0, 1);
73 #elif defined(CONFIG_MACH_SUN8I)
74 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
75 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
76 clock_twi_onoff(0, 1);
77 #elif defined(CONFIG_MACH_SUN50I)
78 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
79 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
80 clock_twi_onoff(0, 1);
84 #ifdef CONFIG_I2C1_ENABLE
85 #if defined(CONFIG_MACH_SUN4I) || \
86 defined(CONFIG_MACH_SUN7I) || \
87 defined(CONFIG_MACH_SUN8I_R40)
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
90 clock_twi_onoff(1, 1);
91 #elif defined(CONFIG_MACH_SUN5I)
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
94 clock_twi_onoff(1, 1);
95 #elif defined(CONFIG_MACH_SUN6I)
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
98 clock_twi_onoff(1, 1);
99 #elif defined(CONFIG_MACH_SUN8I)
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
102 clock_twi_onoff(1, 1);
103 #elif defined(CONFIG_MACH_SUN50I)
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
106 clock_twi_onoff(1, 1);
110 #ifdef CONFIG_R_I2C_ENABLE
111 #ifdef CONFIG_MACH_SUN50I
112 clock_twi_onoff(5, 1);
113 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
114 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
115 #elif CONFIG_MACH_SUN50I_H616
116 clock_twi_onoff(5, 1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
118 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
120 clock_twi_onoff(5, 1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
122 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
128 * Try to use the environment from the boot source first.
129 * For MMC, this means a FAT partition on the boot device (SD or eMMC).
130 * If the raw MMC environment is also enabled, this is tried next.
131 * SPI flash falls back to FAT (on SD card).
133 enum env_location env_get_location(enum env_operation op, int prio)
135 enum env_location boot_loc = ENVL_FAT;
137 gd->env_load_prio = prio;
139 switch (sunxi_get_boot_device()) {
140 case BOOT_DEVICE_MMC1:
141 case BOOT_DEVICE_MMC2:
144 case BOOT_DEVICE_NAND:
145 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
146 boot_loc = ENVL_NAND;
148 case BOOT_DEVICE_SPI:
149 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
150 boot_loc = ENVL_SPI_FLASH;
152 case BOOT_DEVICE_BOARD:
158 /* Always try to access the environment on the boot device first. */
167 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
179 static void mmc_pinmux_setup(int sdc);
182 /* add board specific code here */
185 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
187 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
189 #if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
190 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
191 debug("id_pfr1: 0x%08x\n", id_pfr1);
192 /* Generic Timer Extension available? */
193 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
196 debug("Setting CNTFRQ\n");
199 * CNTFRQ is a secure register, so we will crash if we try to
200 * write this from the non-secure world (read is OK, though).
201 * In case some bootcode has already set the correct value,
202 * we avoid the risk of writing to it.
204 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
205 if (freq != CONFIG_COUNTER_FREQUENCY) {
206 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
207 freq, CONFIG_COUNTER_FREQUENCY);
208 #ifdef CONFIG_NON_SECURE
209 printf("arch timer frequency is wrong, but cannot adjust it\n");
211 asm volatile("mcr p15, 0, %0, c14, c0, 0"
212 : : "r"(CONFIG_COUNTER_FREQUENCY));
216 #endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
218 ret = axp_gpio_init();
222 /* strcmp() would look better, but doesn't get optimised away. */
223 if (CONFIG_SATAPWR[0]) {
224 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
225 if (satapwr_pin >= 0) {
226 gpio_request(satapwr_pin, "satapwr");
227 gpio_direction_output(satapwr_pin, 1);
230 * Give the attached SATA device time to power-up
231 * to avoid link timeouts
237 if (CONFIG_MACPWR[0]) {
238 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
239 if (macpwr_pin >= 0) {
240 gpio_request(macpwr_pin, "macpwr");
241 gpio_direction_output(macpwr_pin, 1);
245 #if CONFIG_IS_ENABLED(DM_I2C)
247 * Temporary workaround for enabling I2C clocks until proper sunxi DM
248 * clk, reset and pinctrl drivers land.
259 * On older SoCs the SPL is actually at address zero, so using NULL as
260 * an error value does not work.
262 #define INVALID_SPL_HEADER ((void *)~0UL)
264 static struct boot_file_head * get_spl_header(uint8_t req_version)
266 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
267 uint8_t spl_header_version = spl->spl_signature[3];
269 /* Is there really the SPL header (still) there? */
270 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
271 return INVALID_SPL_HEADER;
273 if (spl_header_version < req_version) {
274 printf("sunxi SPL version mismatch: expected %u, got %u\n",
275 req_version, spl_header_version);
276 return INVALID_SPL_HEADER;
282 static const char *get_spl_dt_name(void)
284 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
286 /* Check if there is a DT name stored in the SPL header. */
287 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
288 return (char *)spl + spl->dt_name_offset;
295 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
297 if (spl == INVALID_SPL_HEADER)
298 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
301 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
303 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
304 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
309 #if defined(CONFIG_NAND_SUNXI)
310 static void nand_pinmux_setup(void)
314 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
315 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
317 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
318 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
319 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
321 /* sun4i / sun7i do have a PC23, but it is not used for nand,
322 * only sun7i has a PC24 */
323 #ifdef CONFIG_MACH_SUN7I
324 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
328 static void nand_clock_setup(void)
330 struct sunxi_ccm_reg *const ccm =
331 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
333 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
334 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
335 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
336 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
338 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
341 void board_nand_init(void)
345 #ifndef CONFIG_SPL_BUILD
352 static void mmc_pinmux_setup(int sdc)
359 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
360 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
361 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
362 sunxi_gpio_set_drv(pin, 2);
367 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
368 defined(CONFIG_MACH_SUN8I_R40)
369 if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
370 /* SDC1: PH22-PH-27 */
371 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
372 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
373 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
374 sunxi_gpio_set_drv(pin, 2);
378 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
379 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
380 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
381 sunxi_gpio_set_drv(pin, 2);
384 #elif defined(CONFIG_MACH_SUN5I)
386 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
387 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
388 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
389 sunxi_gpio_set_drv(pin, 2);
391 #elif defined(CONFIG_MACH_SUN6I)
393 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
394 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
395 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
396 sunxi_gpio_set_drv(pin, 2);
398 #elif defined(CONFIG_MACH_SUN8I)
400 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
401 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
402 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
403 sunxi_gpio_set_drv(pin, 2);
409 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
411 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
412 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
413 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
414 sunxi_gpio_set_drv(pin, 2);
416 #elif defined(CONFIG_MACH_SUN5I)
418 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
419 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
420 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
421 sunxi_gpio_set_drv(pin, 2);
423 #elif defined(CONFIG_MACH_SUN6I)
424 /* SDC2: PC6-PC15, PC24 */
425 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
426 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
427 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
428 sunxi_gpio_set_drv(pin, 2);
431 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
432 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
433 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
434 #elif defined(CONFIG_MACH_SUN8I_R40)
435 /* SDC2: PC6-PC15, PC24 */
436 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
437 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
438 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
439 sunxi_gpio_set_drv(pin, 2);
442 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
443 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
444 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
445 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
446 /* SDC2: PC5-PC6, PC8-PC16 */
447 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
448 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
449 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
450 sunxi_gpio_set_drv(pin, 2);
453 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
454 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
455 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
456 sunxi_gpio_set_drv(pin, 2);
458 #elif defined(CONFIG_MACH_SUN50I_H6)
460 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
461 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
462 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
463 sunxi_gpio_set_drv(pin, 2);
465 #elif defined(CONFIG_MACH_SUN50I_H616)
466 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
467 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
468 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
470 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
472 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
473 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
474 sunxi_gpio_set_drv(pin, 3);
476 #elif defined(CONFIG_MACH_SUN9I)
478 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
479 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
480 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
481 sunxi_gpio_set_drv(pin, 2);
484 puts("ERROR: No pinmux setup defined for MMC2!\n");
489 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
490 defined(CONFIG_MACH_SUN8I_R40)
492 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
493 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
494 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
495 sunxi_gpio_set_drv(pin, 2);
497 #elif defined(CONFIG_MACH_SUN6I)
498 /* SDC3: PC6-PC15, PC24 */
499 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
500 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
501 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
502 sunxi_gpio_set_drv(pin, 2);
505 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
506 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
507 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
512 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
517 int board_mmc_init(struct bd_info *bis)
519 __maybe_unused struct mmc *mmc0, *mmc1;
521 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
522 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
526 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
527 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
528 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
536 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
537 int mmc_get_env_dev(void)
539 switch (sunxi_get_boot_device()) {
540 case BOOT_DEVICE_MMC1:
542 case BOOT_DEVICE_MMC2:
545 return CONFIG_SYS_MMC_ENV_DEV;
551 #ifdef CONFIG_SPL_BUILD
553 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
555 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
557 if (spl == INVALID_SPL_HEADER)
560 /* Promote the header version for U-Boot proper, if needed. */
561 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
562 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
564 spl->dram_size = dram_size >> 20;
567 void sunxi_board_init(void)
569 int power_failed = 0;
571 #ifdef CONFIG_LED_STATUS
572 if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
576 #ifdef CONFIG_SY8106A_POWER
577 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
580 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
581 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
582 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
583 power_failed = axp_init();
585 if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
588 pmic_bus_read(AXP_POWER_STATUS, &boot_reason);
589 if (boot_reason & AXP_POWER_STATUS_ALDO_IN) {
590 printf("Power on by plug-in, shutting down.\n");
591 pmic_bus_write(0x32, BIT(7));
595 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
596 defined CONFIG_AXP818_POWER
597 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
599 #if !defined(CONFIG_AXP305_POWER)
600 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
601 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
603 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
604 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
606 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
607 defined CONFIG_AXP818_POWER
608 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
611 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
612 defined CONFIG_AXP818_POWER
613 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
615 #if !defined(CONFIG_AXP305_POWER)
616 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
618 #if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
619 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
621 #ifdef CONFIG_AXP209_POWER
622 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
625 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
626 defined(CONFIG_AXP818_POWER)
627 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
628 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
629 #if !defined CONFIG_AXP809_POWER
630 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
631 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
633 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
634 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
635 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
638 #ifdef CONFIG_AXP818_POWER
639 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
640 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
641 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
644 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
645 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
649 gd->ram_size = sunxi_dram_init();
650 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
654 sunxi_spl_store_dram_size(gd->ram_size);
657 * Only clock up the CPU to full speed if we are reasonably
658 * assured it's being powered with suitable core voltage
661 clock_set_pll1(get_board_sys_clk());
663 printf("Failed to set core voltage! Can't set CPU frequency\n");
667 #ifdef CONFIG_USB_GADGET
668 int g_dnl_board_usb_cable_connected(void)
674 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
676 pr_err("%s: Cannot find USB device\n", __func__);
680 ret = generic_phy_get_by_name(dev, "usb", &phy);
682 pr_err("failed to get %s USB PHY\n", dev->name);
686 ret = generic_phy_init(&phy);
688 pr_debug("failed to init %s USB PHY\n", dev->name);
692 return sun4i_usb_phy_vbus_detect(&phy);
696 #ifdef CONFIG_SERIAL_TAG
697 void get_board_serial(struct tag_serialnr *serialnr)
700 unsigned long long serial;
702 serial_string = env_get("serial#");
705 serial = simple_strtoull(serial_string, NULL, 16);
707 serialnr->high = (unsigned int) (serial >> 32);
708 serialnr->low = (unsigned int) (serial & 0xffffffff);
717 * Check the SPL header for the "sunxi" variant. If found: parse values
718 * that might have been passed by the loader ("fel" utility), and update
719 * the environment accordingly.
721 static void parse_spl_header(const uint32_t spl_addr)
723 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
725 if (spl == INVALID_SPL_HEADER)
728 if (!spl->fel_script_address)
731 if (spl->fel_uEnv_length != 0) {
733 * data is expected in uEnv.txt compatible format, so "env
734 * import -t" the string(s) at fel_script_address right away.
736 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
737 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
740 /* otherwise assume .scr format (mkimage-type script) */
741 env_set_hex("fel_scriptaddr", spl->fel_script_address);
744 static bool get_unique_sid(unsigned int *sid)
746 if (sunxi_get_sid(sid) != 0)
753 * The single words 1 - 3 of the SID have quite a few bits
754 * which are the same on many models, so we take a crc32
755 * of all 3 words, to get a more unique value.
757 * Note we only do this on newer SoCs as we cannot change
758 * the algorithm on older SoCs since those have been using
759 * fixed mac-addresses based on only using word 3 for a
760 * long time and changing a fixed mac-address with an
761 * u-boot update is not good.
763 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
764 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
765 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
766 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
769 /* Ensure the NIC specific bytes of the mac are not all 0 */
770 if ((sid[3] & 0xffffff) == 0)
777 * Note this function gets called multiple times.
778 * It must not make any changes to env variables which already exist.
780 static void setup_environment(const void *fdt)
782 char serial_string[17] = { 0 };
788 if (!get_unique_sid(sid))
791 for (i = 0; i < 4; i++) {
792 sprintf(ethaddr, "ethernet%d", i);
793 if (!fdt_get_alias(fdt, ethaddr))
797 strcpy(ethaddr, "ethaddr");
799 sprintf(ethaddr, "eth%daddr", i);
801 if (env_get(ethaddr))
804 /* Non OUI / registered MAC address */
805 mac_addr[0] = (i << 4) | 0x02;
806 mac_addr[1] = (sid[0] >> 0) & 0xff;
807 mac_addr[2] = (sid[3] >> 24) & 0xff;
808 mac_addr[3] = (sid[3] >> 16) & 0xff;
809 mac_addr[4] = (sid[3] >> 8) & 0xff;
810 mac_addr[5] = (sid[3] >> 0) & 0xff;
812 eth_env_set_enetaddr(ethaddr, mac_addr);
815 if (!env_get("serial#")) {
816 snprintf(serial_string, sizeof(serial_string),
817 "%08x%08x", sid[0], sid[3]);
819 env_set("serial#", serial_string);
823 int misc_init_r(void)
825 const char *spl_dt_name;
828 env_set("fel_booted", NULL);
829 env_set("fel_scriptaddr", NULL);
830 env_set("mmc_bootdev", NULL);
832 boot = sunxi_get_boot_device();
833 /* determine if we are running in FEL mode */
834 if (boot == BOOT_DEVICE_BOARD) {
835 env_set("fel_booted", "1");
836 parse_spl_header(SPL_ADDR);
837 /* or if we booted from MMC, and which one */
838 } else if (boot == BOOT_DEVICE_MMC1) {
839 env_set("mmc_bootdev", "0");
840 } else if (boot == BOOT_DEVICE_MMC2) {
841 env_set("mmc_bootdev", "1");
844 /* Set fdtfile to match the FIT configuration chosen in SPL. */
845 spl_dt_name = get_spl_dt_name();
847 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
850 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
851 env_set("fdtfile", str);
854 setup_environment(gd->fdt_blob);
859 int board_late_init(void)
861 #ifdef CONFIG_USB_ETHER
868 static void bluetooth_dt_fixup(void *blob)
870 /* Some devices ship with a Bluetooth controller default address.
871 * Set a valid address through the device tree.
873 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
877 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
880 if (eth_env_get_enetaddr("bdaddr", tmp)) {
881 /* Convert between the binary formats of the corresponding stacks */
882 for (i = 0; i < ETH_ALEN; ++i)
883 bdaddr[i] = tmp[ETH_ALEN - i - 1];
885 if (!get_unique_sid(sid))
888 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
889 bdaddr[1] = (sid[3] >> 8) & 0xff;
890 bdaddr[2] = (sid[3] >> 16) & 0xff;
891 bdaddr[3] = (sid[3] >> 24) & 0xff;
892 bdaddr[4] = (sid[0] >> 0) & 0xff;
896 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
897 "local-bd-address", bdaddr, ETH_ALEN, 1);
900 int ft_board_setup(void *blob, struct bd_info *bd)
902 int __maybe_unused r;
905 * Call setup_environment and fdt_fixup_ethernet again
906 * in case the boot fdt has ethernet aliases the u-boot
907 * copy does not have.
909 setup_environment(blob);
910 fdt_fixup_ethernet(blob);
912 bluetooth_dt_fixup(blob);
914 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
915 r = sunxi_simplefb_setup(blob);
922 #ifdef CONFIG_SPL_LOAD_FIT
924 static void set_spl_dt_name(const char *name)
926 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
928 if (spl == INVALID_SPL_HEADER)
931 /* Promote the header version for U-Boot proper, if needed. */
932 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
933 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
935 strcpy((char *)&spl->string_pool, name);
936 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
939 int board_fit_config_name_match(const char *name)
941 const char *best_dt_name = get_spl_dt_name();
944 #ifdef CONFIG_DEFAULT_DEVICE_TREE
945 if (best_dt_name == NULL)
946 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
949 if (best_dt_name == NULL) {
950 /* No DT name was provided, so accept the first config. */
953 #ifdef CONFIG_PINE64_DT_SELECTION
954 if (strstr(best_dt_name, "-pine64-plus")) {
955 /* Differentiate the Pine A64 boards by their DRAM size. */
956 if ((gd->ram_size == 512 * 1024 * 1024))
957 best_dt_name = "sun50i-a64-pine64";
960 #ifdef CONFIG_PINEPHONE_DT_SELECTION
961 if (strstr(best_dt_name, "-pinephone")) {
962 /* Differentiate the PinePhone revisions by GPIO inputs. */
963 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
964 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
965 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
968 /* PL6 is pulled low by the modem on v1.2. */
969 if (gpio_get_value(SUNXI_GPL(6)) == 0)
970 best_dt_name = "sun50i-a64-pinephone-1.2";
972 best_dt_name = "sun50i-a64-pinephone-1.1";
974 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
975 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
976 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
980 ret = strcmp(name, best_dt_name);
983 * If one of the FIT configurations matches the most accurate DT name,
984 * update the SPL header to provide that DT name to U-Boot proper.
987 set_spl_dt_name(best_dt_name);