1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
22 #include <generic-phy.h>
23 #include <phy-sun4i-usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/display.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/spl.h>
32 #include <asm/global_data.h>
33 #include <linux/delay.h>
34 #include <u-boot/crc.h>
36 #include <asm/armv7.h>
40 #include <u-boot/crc.h>
41 #include <env_internal.h>
42 #include <linux/libfdt.h>
43 #include <fdt_support.h>
48 #include <asm/setup.h>
50 #if defined(CONFIG_VIDEO_LCD_PANEL_I2C)
51 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
52 int soft_i2c_gpio_sda;
53 int soft_i2c_gpio_scl;
55 static int soft_i2c_board_init(void)
59 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
60 if (soft_i2c_gpio_sda < 0) {
61 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
63 return soft_i2c_gpio_sda;
65 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
67 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
72 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
73 if (soft_i2c_gpio_scl < 0) {
74 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
75 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
76 return soft_i2c_gpio_scl;
78 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
80 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
81 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
88 static int soft_i2c_board_init(void) { return 0; }
91 DECLARE_GLOBAL_DATA_PTR;
93 void i2c_init_board(void)
95 #ifdef CONFIG_I2C0_ENABLE
96 #if defined(CONFIG_MACH_SUN4I) || \
97 defined(CONFIG_MACH_SUN5I) || \
98 defined(CONFIG_MACH_SUN7I) || \
99 defined(CONFIG_MACH_SUN8I_R40)
100 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
102 clock_twi_onoff(0, 1);
103 #elif defined(CONFIG_MACH_SUN6I)
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
106 clock_twi_onoff(0, 1);
107 #elif defined(CONFIG_MACH_SUN8I_V3S)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
110 clock_twi_onoff(0, 1);
111 #elif defined(CONFIG_MACH_SUN8I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
114 clock_twi_onoff(0, 1);
115 #elif defined(CONFIG_MACH_SUN50I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
118 clock_twi_onoff(0, 1);
122 #ifdef CONFIG_I2C1_ENABLE
123 #if defined(CONFIG_MACH_SUN4I) || \
124 defined(CONFIG_MACH_SUN7I) || \
125 defined(CONFIG_MACH_SUN8I_R40)
126 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
127 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
128 clock_twi_onoff(1, 1);
129 #elif defined(CONFIG_MACH_SUN5I)
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
132 clock_twi_onoff(1, 1);
133 #elif defined(CONFIG_MACH_SUN6I)
134 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
135 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
136 clock_twi_onoff(1, 1);
137 #elif defined(CONFIG_MACH_SUN8I)
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
140 clock_twi_onoff(1, 1);
141 #elif defined(CONFIG_MACH_SUN50I)
142 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
143 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
144 clock_twi_onoff(1, 1);
148 #ifdef CONFIG_I2C2_ENABLE
149 #if defined(CONFIG_MACH_SUN4I) || \
150 defined(CONFIG_MACH_SUN7I) || \
151 defined(CONFIG_MACH_SUN8I_R40)
152 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
153 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
154 clock_twi_onoff(2, 1);
155 #elif defined(CONFIG_MACH_SUN5I)
156 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
157 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
158 clock_twi_onoff(2, 1);
159 #elif defined(CONFIG_MACH_SUN6I)
160 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
161 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
162 clock_twi_onoff(2, 1);
163 #elif defined(CONFIG_MACH_SUN8I)
164 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
165 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
166 clock_twi_onoff(2, 1);
167 #elif defined(CONFIG_MACH_SUN50I)
168 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
169 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
170 clock_twi_onoff(2, 1);
174 #ifdef CONFIG_I2C3_ENABLE
175 #if defined(CONFIG_MACH_SUN6I)
176 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
177 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
178 clock_twi_onoff(3, 1);
179 #elif defined(CONFIG_MACH_SUN7I) || \
180 defined(CONFIG_MACH_SUN8I_R40)
181 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
182 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
183 clock_twi_onoff(3, 1);
187 #ifdef CONFIG_I2C4_ENABLE
188 #if defined(CONFIG_MACH_SUN7I) || \
189 defined(CONFIG_MACH_SUN8I_R40)
190 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
191 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
192 clock_twi_onoff(4, 1);
196 #ifdef CONFIG_R_I2C_ENABLE
197 #ifdef CONFIG_MACH_SUN50I
198 clock_twi_onoff(5, 1);
199 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
200 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
201 #elif CONFIG_MACH_SUN50I_H616
202 clock_twi_onoff(5, 1);
203 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
204 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
206 clock_twi_onoff(5, 1);
207 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
208 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
213 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
214 enum env_location env_get_location(enum env_operation op, int prio)
230 static void mmc_pinmux_setup(int sdc);
233 /* add board specific code here */
236 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
238 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
241 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
242 debug("id_pfr1: 0x%08x\n", id_pfr1);
243 /* Generic Timer Extension available? */
244 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
247 debug("Setting CNTFRQ\n");
250 * CNTFRQ is a secure register, so we will crash if we try to
251 * write this from the non-secure world (read is OK, though).
252 * In case some bootcode has already set the correct value,
253 * we avoid the risk of writing to it.
255 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
256 if (freq != COUNTER_FREQUENCY) {
257 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
258 freq, COUNTER_FREQUENCY);
259 #ifdef CONFIG_NON_SECURE
260 printf("arch timer frequency is wrong, but cannot adjust it\n");
262 asm volatile("mcr p15, 0, %0, c14, c0, 0"
263 : : "r"(COUNTER_FREQUENCY));
267 #endif /* !CONFIG_ARM64 */
269 ret = axp_gpio_init();
273 /* strcmp() would look better, but doesn't get optimised away. */
274 if (CONFIG_SATAPWR[0]) {
275 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
276 if (satapwr_pin >= 0) {
277 gpio_request(satapwr_pin, "satapwr");
278 gpio_direction_output(satapwr_pin, 1);
281 * Give the attached SATA device time to power-up
282 * to avoid link timeouts
288 if (CONFIG_MACPWR[0]) {
289 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
290 if (macpwr_pin >= 0) {
291 gpio_request(macpwr_pin, "macpwr");
292 gpio_direction_output(macpwr_pin, 1);
296 #if CONFIG_IS_ENABLED(DM_I2C)
298 * Temporary workaround for enabling I2C clocks until proper sunxi DM
299 * clk, reset and pinctrl drivers land.
306 * Temporary workaround for enabling MMC clocks until a sunxi DM
307 * pinctrl driver lands.
309 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
310 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
311 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
313 #endif /* CONFIG_DM_MMC */
315 /* Uses dm gpio code so do this here and not in i2c_init_board() */
316 return soft_i2c_board_init();
320 * On older SoCs the SPL is actually at address zero, so using NULL as
321 * an error value does not work.
323 #define INVALID_SPL_HEADER ((void *)~0UL)
325 static struct boot_file_head * get_spl_header(uint8_t req_version)
327 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
328 uint8_t spl_header_version = spl->spl_signature[3];
330 /* Is there really the SPL header (still) there? */
331 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
332 return INVALID_SPL_HEADER;
334 if (spl_header_version < req_version) {
335 printf("sunxi SPL version mismatch: expected %u, got %u\n",
336 req_version, spl_header_version);
337 return INVALID_SPL_HEADER;
343 static const char *get_spl_dt_name(void)
345 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
347 /* Check if there is a DT name stored in the SPL header. */
348 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
349 return (char *)spl + spl->dt_name_offset;
356 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
358 if (spl == INVALID_SPL_HEADER)
359 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
362 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
364 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
365 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
370 #if defined(CONFIG_NAND_SUNXI)
371 static void nand_pinmux_setup(void)
375 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
376 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
378 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
379 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
380 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
382 /* sun4i / sun7i do have a PC23, but it is not used for nand,
383 * only sun7i has a PC24 */
384 #ifdef CONFIG_MACH_SUN7I
385 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
389 static void nand_clock_setup(void)
391 struct sunxi_ccm_reg *const ccm =
392 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
394 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
395 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
396 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
397 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
399 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
402 void board_nand_init(void)
406 #ifndef CONFIG_SPL_BUILD
413 static void mmc_pinmux_setup(int sdc)
416 __maybe_unused int pins;
421 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
422 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
423 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
424 sunxi_gpio_set_drv(pin, 2);
429 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
431 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
432 defined(CONFIG_MACH_SUN8I_R40)
433 if (pins == SUNXI_GPIO_H) {
434 /* SDC1: PH22-PH-27 */
435 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
436 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
437 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
438 sunxi_gpio_set_drv(pin, 2);
442 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
443 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
444 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
445 sunxi_gpio_set_drv(pin, 2);
448 #elif defined(CONFIG_MACH_SUN5I)
450 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
451 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
452 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
453 sunxi_gpio_set_drv(pin, 2);
455 #elif defined(CONFIG_MACH_SUN6I)
457 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
458 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
459 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
460 sunxi_gpio_set_drv(pin, 2);
462 #elif defined(CONFIG_MACH_SUN8I)
463 if (pins == SUNXI_GPIO_D) {
465 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
466 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
467 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
468 sunxi_gpio_set_drv(pin, 2);
472 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
473 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
474 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
475 sunxi_gpio_set_drv(pin, 2);
482 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
484 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
486 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
487 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
488 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
489 sunxi_gpio_set_drv(pin, 2);
491 #elif defined(CONFIG_MACH_SUN5I)
492 if (pins == SUNXI_GPIO_E) {
494 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
495 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
496 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
497 sunxi_gpio_set_drv(pin, 2);
501 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
502 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
503 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
504 sunxi_gpio_set_drv(pin, 2);
507 #elif defined(CONFIG_MACH_SUN6I)
508 if (pins == SUNXI_GPIO_A) {
510 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
511 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
512 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
513 sunxi_gpio_set_drv(pin, 2);
516 /* SDC2: PC6-PC15, PC24 */
517 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
518 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
519 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
520 sunxi_gpio_set_drv(pin, 2);
523 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
524 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
525 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
527 #elif defined(CONFIG_MACH_SUN8I_R40)
528 /* SDC2: PC6-PC15, PC24 */
529 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
530 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
531 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
532 sunxi_gpio_set_drv(pin, 2);
535 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
536 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
537 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
538 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
539 /* SDC2: PC5-PC6, PC8-PC16 */
540 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
541 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
542 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
543 sunxi_gpio_set_drv(pin, 2);
546 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
547 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
548 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
549 sunxi_gpio_set_drv(pin, 2);
551 #elif defined(CONFIG_MACH_SUN50I_H6)
553 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
554 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
555 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
556 sunxi_gpio_set_drv(pin, 2);
558 #elif defined(CONFIG_MACH_SUN50I_H616)
559 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
560 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
561 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
563 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
565 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
566 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
567 sunxi_gpio_set_drv(pin, 3);
569 #elif defined(CONFIG_MACH_SUN9I)
571 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
572 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
573 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
574 sunxi_gpio_set_drv(pin, 2);
577 puts("ERROR: No pinmux setup defined for MMC2!\n");
582 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
584 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
585 defined(CONFIG_MACH_SUN8I_R40)
587 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
588 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
589 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
590 sunxi_gpio_set_drv(pin, 2);
592 #elif defined(CONFIG_MACH_SUN6I)
593 if (pins == SUNXI_GPIO_A) {
595 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
596 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
597 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
598 sunxi_gpio_set_drv(pin, 2);
601 /* SDC3: PC6-PC15, PC24 */
602 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
603 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
604 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
605 sunxi_gpio_set_drv(pin, 2);
608 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
609 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
610 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
616 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
621 int board_mmc_init(struct bd_info *bis)
623 __maybe_unused struct mmc *mmc0, *mmc1;
625 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
626 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
630 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
631 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
632 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
640 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
641 int mmc_get_env_dev(void)
643 switch (sunxi_get_boot_device()) {
644 case BOOT_DEVICE_MMC1:
646 case BOOT_DEVICE_MMC2:
649 return CONFIG_SYS_MMC_ENV_DEV;
655 #ifdef CONFIG_SPL_BUILD
657 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
659 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
661 if (spl == INVALID_SPL_HEADER)
664 /* Promote the header version for U-Boot proper, if needed. */
665 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
666 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
668 spl->dram_size = dram_size >> 20;
671 void sunxi_board_init(void)
673 int power_failed = 0;
675 #ifdef CONFIG_SY8106A_POWER
676 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
679 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
680 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
681 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
682 power_failed = axp_init();
684 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
685 defined CONFIG_AXP818_POWER
686 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
688 #if !defined(CONFIG_AXP305_POWER)
689 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
690 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
692 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
693 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
695 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
696 defined CONFIG_AXP818_POWER
697 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
700 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
701 defined CONFIG_AXP818_POWER
702 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
704 #if !defined(CONFIG_AXP305_POWER)
705 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
707 #if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
708 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
710 #ifdef CONFIG_AXP209_POWER
711 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
714 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
715 defined(CONFIG_AXP818_POWER)
716 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
717 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
718 #if !defined CONFIG_AXP809_POWER
719 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
720 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
722 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
723 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
724 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
727 #ifdef CONFIG_AXP818_POWER
728 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
729 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
730 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
733 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
734 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
738 gd->ram_size = sunxi_dram_init();
739 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
743 sunxi_spl_store_dram_size(gd->ram_size);
746 * Only clock up the CPU to full speed if we are reasonably
747 * assured it's being powered with suitable core voltage
750 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
752 printf("Failed to set core voltage! Can't set CPU frequency\n");
756 #ifdef CONFIG_USB_GADGET
757 int g_dnl_board_usb_cable_connected(void)
763 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
765 pr_err("%s: Cannot find USB device\n", __func__);
769 ret = generic_phy_get_by_name(dev, "usb", &phy);
771 pr_err("failed to get %s USB PHY\n", dev->name);
775 ret = generic_phy_init(&phy);
777 pr_debug("failed to init %s USB PHY\n", dev->name);
781 ret = sun4i_usb_phy_vbus_detect(&phy);
783 pr_err("A charger is plugged into the OTG\n");
791 #ifdef CONFIG_SERIAL_TAG
792 void get_board_serial(struct tag_serialnr *serialnr)
795 unsigned long long serial;
797 serial_string = env_get("serial#");
800 serial = simple_strtoull(serial_string, NULL, 16);
802 serialnr->high = (unsigned int) (serial >> 32);
803 serialnr->low = (unsigned int) (serial & 0xffffffff);
812 * Check the SPL header for the "sunxi" variant. If found: parse values
813 * that might have been passed by the loader ("fel" utility), and update
814 * the environment accordingly.
816 static void parse_spl_header(const uint32_t spl_addr)
818 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
820 if (spl == INVALID_SPL_HEADER)
823 if (!spl->fel_script_address)
826 if (spl->fel_uEnv_length != 0) {
828 * data is expected in uEnv.txt compatible format, so "env
829 * import -t" the string(s) at fel_script_address right away.
831 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
832 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
835 /* otherwise assume .scr format (mkimage-type script) */
836 env_set_hex("fel_scriptaddr", spl->fel_script_address);
839 static bool get_unique_sid(unsigned int *sid)
841 if (sunxi_get_sid(sid) != 0)
848 * The single words 1 - 3 of the SID have quite a few bits
849 * which are the same on many models, so we take a crc32
850 * of all 3 words, to get a more unique value.
852 * Note we only do this on newer SoCs as we cannot change
853 * the algorithm on older SoCs since those have been using
854 * fixed mac-addresses based on only using word 3 for a
855 * long time and changing a fixed mac-address with an
856 * u-boot update is not good.
858 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
859 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
860 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
861 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
864 /* Ensure the NIC specific bytes of the mac are not all 0 */
865 if ((sid[3] & 0xffffff) == 0)
872 * Note this function gets called multiple times.
873 * It must not make any changes to env variables which already exist.
875 static void setup_environment(const void *fdt)
877 char serial_string[17] = { 0 };
883 if (!get_unique_sid(sid))
886 for (i = 0; i < 4; i++) {
887 sprintf(ethaddr, "ethernet%d", i);
888 if (!fdt_get_alias(fdt, ethaddr))
892 strcpy(ethaddr, "ethaddr");
894 sprintf(ethaddr, "eth%daddr", i);
896 if (env_get(ethaddr))
899 /* Non OUI / registered MAC address */
900 mac_addr[0] = (i << 4) | 0x02;
901 mac_addr[1] = (sid[0] >> 0) & 0xff;
902 mac_addr[2] = (sid[3] >> 24) & 0xff;
903 mac_addr[3] = (sid[3] >> 16) & 0xff;
904 mac_addr[4] = (sid[3] >> 8) & 0xff;
905 mac_addr[5] = (sid[3] >> 0) & 0xff;
907 eth_env_set_enetaddr(ethaddr, mac_addr);
910 if (!env_get("serial#")) {
911 snprintf(serial_string, sizeof(serial_string),
912 "%08x%08x", sid[0], sid[3]);
914 env_set("serial#", serial_string);
918 int misc_init_r(void)
920 const char *spl_dt_name;
923 env_set("fel_booted", NULL);
924 env_set("fel_scriptaddr", NULL);
925 env_set("mmc_bootdev", NULL);
927 boot = sunxi_get_boot_device();
928 /* determine if we are running in FEL mode */
929 if (boot == BOOT_DEVICE_BOARD) {
930 env_set("fel_booted", "1");
931 parse_spl_header(SPL_ADDR);
932 /* or if we booted from MMC, and which one */
933 } else if (boot == BOOT_DEVICE_MMC1) {
934 env_set("mmc_bootdev", "0");
935 } else if (boot == BOOT_DEVICE_MMC2) {
936 env_set("mmc_bootdev", "1");
939 /* Set fdtfile to match the FIT configuration chosen in SPL. */
940 spl_dt_name = get_spl_dt_name();
942 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
945 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
946 env_set("fdtfile", str);
949 setup_environment(gd->fdt_blob);
954 int board_late_init(void)
956 #ifdef CONFIG_USB_ETHER
963 static void bluetooth_dt_fixup(void *blob)
965 /* Some devices ship with a Bluetooth controller default address.
966 * Set a valid address through the device tree.
968 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
972 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
975 if (eth_env_get_enetaddr("bdaddr", tmp)) {
976 /* Convert between the binary formats of the corresponding stacks */
977 for (i = 0; i < ETH_ALEN; ++i)
978 bdaddr[i] = tmp[ETH_ALEN - i - 1];
980 if (!get_unique_sid(sid))
983 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
984 bdaddr[1] = (sid[3] >> 8) & 0xff;
985 bdaddr[2] = (sid[3] >> 16) & 0xff;
986 bdaddr[3] = (sid[3] >> 24) & 0xff;
987 bdaddr[4] = (sid[0] >> 0) & 0xff;
991 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
992 "local-bd-address", bdaddr, ETH_ALEN, 1);
995 int ft_board_setup(void *blob, struct bd_info *bd)
997 int __maybe_unused r;
1000 * Call setup_environment again in case the boot fdt has
1001 * ethernet aliases the u-boot copy does not have.
1003 setup_environment(blob);
1005 bluetooth_dt_fixup(blob);
1007 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
1008 r = sunxi_simplefb_setup(blob);
1015 #ifdef CONFIG_SPL_LOAD_FIT
1017 static void set_spl_dt_name(const char *name)
1019 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
1021 if (spl == INVALID_SPL_HEADER)
1024 /* Promote the header version for U-Boot proper, if needed. */
1025 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
1026 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
1028 strcpy((char *)&spl->string_pool, name);
1029 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
1032 int board_fit_config_name_match(const char *name)
1034 const char *best_dt_name = get_spl_dt_name();
1037 #ifdef CONFIG_DEFAULT_DEVICE_TREE
1038 if (best_dt_name == NULL)
1039 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
1042 if (best_dt_name == NULL) {
1043 /* No DT name was provided, so accept the first config. */
1046 #ifdef CONFIG_PINE64_DT_SELECTION
1047 if (strstr(best_dt_name, "-pine64-plus")) {
1048 /* Differentiate the Pine A64 boards by their DRAM size. */
1049 if ((gd->ram_size == 512 * 1024 * 1024))
1050 best_dt_name = "sun50i-a64-pine64";
1053 #ifdef CONFIG_PINEPHONE_DT_SELECTION
1054 if (strstr(best_dt_name, "-pinephone")) {
1055 /* Differentiate the PinePhone revisions by GPIO inputs. */
1056 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
1057 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
1058 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
1061 /* PL6 is pulled low by the modem on v1.2. */
1062 if (gpio_get_value(SUNXI_GPL(6)) == 0)
1063 best_dt_name = "sun50i-a64-pinephone-1.2";
1065 best_dt_name = "sun50i-a64-pinephone-1.1";
1067 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
1068 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
1069 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
1073 ret = strcmp(name, best_dt_name);
1076 * If one of the FIT configurations matches the most accurate DT name,
1077 * update the SPL header to provide that DT name to U-Boot proper.
1080 set_spl_dt_name(best_dt_name);