3 # Note only one of these may be selected at a time! But hidden choices are
4 # not supported by Kconfig
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
11 config SUNXI_GEN_SUN6I
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
20 prompt "Sunxi SoC Variant"
24 bool "sun4i (Allwinner A10)"
26 select SUNXI_GEN_SUN4I
30 bool "sun5i (Allwinner A13)"
32 select SUNXI_GEN_SUN4I
36 bool "sun6i (Allwinner A31)"
38 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
40 select SUNXI_GEN_SUN6I
42 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
45 bool "sun7i (Allwinner A20)"
47 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
49 select SUNXI_GEN_SUN4I
51 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
54 bool "sun8i (Allwinner A23)"
56 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
58 select SUNXI_GEN_SUN6I
60 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
63 bool "sun8i (Allwinner A33)"
65 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
67 select SUNXI_GEN_SUN6I
69 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
72 bool "sun8i (Allwinner H3)"
74 select SUNXI_GEN_SUN6I
77 config MACH_SUN8I_A83T
78 bool "sun8i (Allwinner A83T)"
80 select SUNXI_GEN_SUN6I
84 bool "sun9i (Allwinner A80)"
86 select SUNXI_GEN_SUN6I
90 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
93 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
97 int "sunxi dram clock speed"
98 default 312 if MACH_SUN6I || MACH_SUN8I
99 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
101 Set the dram clock speed, valid range 240 - 480, must be a multiple
104 if MACH_SUN5I || MACH_SUN7I
106 int "sunxi mbus clock speed"
109 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
114 int "sunxi dram zq value"
115 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
116 default 127 if MACH_SUN7I
118 Set the dram zq value.
121 bool "sunxi dram odt enable"
122 default n if !MACH_SUN8I_A23
123 default y if MACH_SUN8I_A23
125 Select this to enable dram odt (on die termination).
127 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
129 int "sunxi dram emr1 value"
130 default 0 if MACH_SUN4I
131 default 4 if MACH_SUN5I || MACH_SUN7I
133 Set the dram controller emr1 value.
136 hex "sunxi dram tpr3 value"
139 Set the dram controller tpr3 parameter. This parameter configures
140 the delay on the command lane and also phase shifts, which are
141 applied for sampling incoming read data. The default value 0
142 means that no phase/delay adjustments are necessary. Properly
143 configuring this parameter increases reliability at high DRAM
146 config DRAM_DQS_GATING_DELAY
147 hex "sunxi dram dqs_gating_delay value"
150 Set the dram controller dqs_gating_delay parmeter. Each byte
151 encodes the DQS gating delay for each byte lane. The delay
152 granularity is 1/4 cycle. For example, the value 0x05060606
153 means that the delay is 5 quarter-cycles for one lane (1.25
154 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
155 The default value 0 means autodetection. The results of hardware
156 autodetection are not very reliable and depend on the chip
157 temperature (sometimes producing different results on cold start
158 and warm reboot). But the accuracy of hardware autodetection
159 is usually good enough, unless running at really high DRAM
160 clocks speeds (up to 600MHz). If unsure, keep as 0.
163 prompt "sunxi dram timings"
164 default DRAM_TIMINGS_VENDOR_MAGIC
166 Select the timings of the DDR3 chips.
168 config DRAM_TIMINGS_VENDOR_MAGIC
169 bool "Magic vendor timings from Android"
171 The same DRAM timings as in the Allwinner boot0 bootloader.
173 config DRAM_TIMINGS_DDR3_1066F_1333H
174 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
176 Use the timings of the standard JEDEC DDR3-1066F speed bin for
177 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
178 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
179 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
180 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
181 that down binning to DDR3-1066F is supported (because DDR3-1066F
182 uses a bit faster timings than DDR3-1333H).
184 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
185 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
187 Use the timings of the slowest possible JEDEC speed bin for the
188 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
189 DDR3-800E, DDR3-1066G or DDR3-1333J.
196 config DRAM_ODT_CORRECTION
197 int "sunxi dram odt correction value"
200 Set the dram odt correction value (range -255 - 255). In allwinner
201 fex files, this option is found in bits 8-15 of the u32 odt_en variable
202 in the [dram] section. When bit 31 of the odt_en variable is set
203 then the correction is negative. Usually the value for this is 0.
207 default 912000000 if MACH_SUN7I
208 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
210 config SYS_CONFIG_NAME
211 default "sun4i" if MACH_SUN4I
212 default "sun5i" if MACH_SUN5I
213 default "sun6i" if MACH_SUN6I
214 default "sun7i" if MACH_SUN7I
215 default "sun8i" if MACH_SUN8I
216 default "sun9i" if MACH_SUN9I
225 bool "UART0 on MicroSD breakout board"
228 Repurpose the SD card slot for getting access to the UART0 serial
229 console. Primarily useful only for low level u-boot debugging on
230 tablets, where normal UART0 is difficult to access and requires
231 device disassembly and/or soldering. As the SD card can't be used
232 at the same time, the system can be only booted in the FEL mode.
233 Only enable this if you really know what you are doing.
235 config OLD_SUNXI_KERNEL_COMPAT
236 boolean "Enable workarounds for booting old kernels"
239 Set this to enable various workarounds for old kernels, this results in
240 sub-optimal settings for newer kernels, only enable if needed.
243 depends on !UART0_PORT_F
244 default y if ARCH_SUNXI
247 string "Card detect pin for mmc0"
250 Set the card detect pin for mmc0, leave empty to not use cd. This
251 takes a string in the format understood by sunxi_name_to_gpio, e.g.
252 PH1 for pin 1 of port H.
255 string "Card detect pin for mmc1"
258 See MMC0_CD_PIN help text.
261 string "Card detect pin for mmc2"
264 See MMC0_CD_PIN help text.
267 string "Card detect pin for mmc3"
270 See MMC0_CD_PIN help text.
273 string "Pins for mmc1"
276 Set the pins used for mmc1, when applicable. This takes a string in the
277 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
280 string "Pins for mmc2"
283 See MMC1_PINS help text.
286 string "Pins for mmc3"
289 See MMC1_PINS help text.
291 config MMC_SUNXI_SLOT_EXTRA
292 int "mmc extra slot number"
295 sunxi builds always enable mmc0, some boards also have a second sdcard
296 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
300 string "Vbus enable pin for usb0 (otg)"
303 Set the Vbus enable pin for usb0 (otg). This takes a string in the
304 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
307 string "Vbus detect pin for usb0 (otg)"
310 Set the Vbus detect pin for usb0 (otg). This takes a string in the
311 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
314 string "ID detect pin for usb0 (otg)"
317 Set the ID detect pin for usb0 (otg). This takes a string in the
318 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
321 string "Vbus enable pin for usb1 (ehci0)"
322 default "PH6" if MACH_SUN4I || MACH_SUN7I
323 default "PH27" if MACH_SUN6I
325 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
326 a string in the format understood by sunxi_name_to_gpio, e.g.
327 PH1 for pin 1 of port H.
330 string "Vbus enable pin for usb2 (ehci1)"
331 default "PH3" if MACH_SUN4I || MACH_SUN7I
332 default "PH24" if MACH_SUN6I
334 See USB1_VBUS_PIN help text.
337 bool "Enable I2C/TWI controller 0"
338 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
339 default n if MACH_SUN6I || MACH_SUN8I
341 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
342 its clock and setting up the bus. This is especially useful on devices
343 with slaves connected to the bus or with pins exposed through e.g. an
344 expansion port/header.
347 bool "Enable I2C/TWI controller 1"
350 See I2C0_ENABLE help text.
353 bool "Enable I2C/TWI controller 2"
356 See I2C0_ENABLE help text.
358 if MACH_SUN6I || MACH_SUN7I
360 bool "Enable I2C/TWI controller 3"
363 See I2C0_ENABLE help text.
368 bool "Enable I2C/TWI controller 4"
371 See I2C0_ENABLE help text.
375 boolean "Enable support for gpio-s on axp PMICs"
378 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
381 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
382 depends on !MACH_SUN8I_A83T
385 Say Y here to add support for using a cfb console on the HDMI, LCD
386 or VGA output found on most sunxi devices. See doc/README.video for
387 info on how to select the video output and mode.
390 boolean "HDMI output support"
391 depends on VIDEO && !MACH_SUN8I
394 Say Y here to add support for outputting video over HDMI.
397 boolean "VGA output support"
398 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
401 Say Y here to add support for outputting video over VGA.
403 config VIDEO_VGA_VIA_LCD
404 boolean "VGA via LCD controller support"
405 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
408 Say Y here to add support for external DACs connected to the parallel
409 LCD interface driving a VGA connector, such as found on the
412 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
413 boolean "Force sync active high for VGA via LCD controller support"
414 depends on VIDEO_VGA_VIA_LCD
417 Say Y here if you've a board which uses opendrain drivers for the vga
418 hsync and vsync signals. Opendrain drivers cannot generate steep enough
419 positive edges for a stable video output, so on boards with opendrain
420 drivers the sync signals must always be active high.
422 config VIDEO_VGA_EXTERNAL_DAC_EN
423 string "LCD panel power enable pin"
424 depends on VIDEO_VGA_VIA_LCD
427 Set the enable pin for the external VGA DAC. This takes a string in the
428 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
430 config VIDEO_COMPOSITE
431 boolean "Composite video output support"
432 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
435 Say Y here to add support for outputting composite video.
437 config VIDEO_LCD_MODE
438 string "LCD panel timing details"
442 LCD panel timing details string, leave empty if there is no LCD panel.
443 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
444 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
445 Also see: http://linux-sunxi.org/LCD
447 config VIDEO_LCD_DCLK_PHASE
448 int "LCD panel display clock phase"
452 Select LCD panel display clock phase shift, range 0-3.
454 config VIDEO_LCD_POWER
455 string "LCD panel power enable pin"
459 Set the power enable pin for the LCD panel. This takes a string in the
460 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
462 config VIDEO_LCD_RESET
463 string "LCD panel reset pin"
467 Set the reset pin for the LCD panel. This takes a string in the format
468 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
470 config VIDEO_LCD_BL_EN
471 string "LCD panel backlight enable pin"
475 Set the backlight enable pin for the LCD panel. This takes a string in the
476 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
479 config VIDEO_LCD_BL_PWM
480 string "LCD panel backlight pwm pin"
484 Set the backlight pwm pin for the LCD panel. This takes a string in the
485 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
487 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
488 bool "LCD panel backlight pwm is inverted"
492 Set this if the backlight pwm output is active low.
494 config VIDEO_LCD_PANEL_I2C
495 bool "LCD panel needs to be configured via i2c"
499 Say y here if the LCD panel needs to be configured via i2c. This
500 will add a bitbang i2c controller using gpios to talk to the LCD.
502 config VIDEO_LCD_PANEL_I2C_SDA
503 string "LCD panel i2c interface SDA pin"
504 depends on VIDEO_LCD_PANEL_I2C
507 Set the SDA pin for the LCD i2c interface. This takes a string in the
508 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
510 config VIDEO_LCD_PANEL_I2C_SCL
511 string "LCD panel i2c interface SCL pin"
512 depends on VIDEO_LCD_PANEL_I2C
515 Set the SCL pin for the LCD i2c interface. This takes a string in the
516 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
519 # Note only one of these may be selected at a time! But hidden choices are
520 # not supported by Kconfig
521 config VIDEO_LCD_IF_PARALLEL
524 config VIDEO_LCD_IF_LVDS
529 prompt "LCD panel support"
532 Select which type of LCD panel to support.
534 config VIDEO_LCD_PANEL_PARALLEL
535 bool "Generic parallel interface LCD panel"
536 select VIDEO_LCD_IF_PARALLEL
538 config VIDEO_LCD_PANEL_LVDS
539 bool "Generic lvds interface LCD panel"
540 select VIDEO_LCD_IF_LVDS
542 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
543 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
544 select VIDEO_LCD_SSD2828
545 select VIDEO_LCD_IF_PARALLEL
547 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
549 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
550 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
551 select VIDEO_LCD_ANX9804
552 select VIDEO_LCD_IF_PARALLEL
553 select VIDEO_LCD_PANEL_I2C
555 Select this for eDP LCD panels with 4 lanes running at 1.62G,
556 connected via an ANX9804 bridge chip.
558 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
559 bool "Hitachi tx18d42vm LCD panel"
560 select VIDEO_LCD_HITACHI_TX18D42VM
561 select VIDEO_LCD_IF_LVDS
563 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
565 config VIDEO_LCD_TL059WV5C0
566 bool "tl059wv5c0 LCD panel"
567 select VIDEO_LCD_PANEL_I2C
568 select VIDEO_LCD_IF_PARALLEL
570 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
571 Aigo M60/M608/M606 tablets.
577 int "GMAC Transmit Clock Delay Chain"
580 Set the GMAC Transmit Clock Delay Chain value.
582 config SPL_STACK_R_ADDR
583 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I
584 default 0x2fe00000 if MACH_SUN9I