4 default " Allwinner Technology"
6 config PRE_CONSOLE_BUFFER
9 config SPL_GPIO_SUPPORT
12 config SPL_LIBCOMMON_SUPPORT
15 config SPL_LIBDISK_SUPPORT
18 config SPL_LIBGENERIC_SUPPORT
21 config SPL_MMC_SUPPORT
24 config SPL_POWER_SUPPORT
27 config SPL_SERIAL_SUPPORT
30 # Note only one of these may be selected at a time! But hidden choices are
31 # not supported by Kconfig
32 config SUNXI_GEN_SUN4I
35 Select this for sunxi SoCs which have resets and clocks set up
36 as the original A10 (mach-sun4i).
38 config SUNXI_GEN_SUN6I
41 Select this for sunxi SoCs which have sun6i like periphery, like
42 separate ahb reset control registers, custom pmic bus, new style
47 prompt "Sunxi SoC Variant"
51 bool "sun4i (Allwinner A10)"
53 select SUNXI_GEN_SUN4I
57 bool "sun5i (Allwinner A13)"
59 select SUNXI_GEN_SUN4I
63 bool "sun6i (Allwinner A31)"
65 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
67 select ARCH_SUPPORT_PSCI
68 select SUNXI_GEN_SUN6I
70 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
73 bool "sun7i (Allwinner A20)"
75 select CPU_V7_HAS_NONSEC
76 select CPU_V7_HAS_VIRT
77 select ARCH_SUPPORT_PSCI
78 select SUNXI_GEN_SUN4I
80 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
83 bool "sun8i (Allwinner A23)"
85 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
87 select ARCH_SUPPORT_PSCI
88 select SUNXI_GEN_SUN6I
90 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
93 bool "sun8i (Allwinner A33)"
95 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
97 select ARCH_SUPPORT_PSCI
98 select SUNXI_GEN_SUN6I
100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
102 config MACH_SUN8I_A83T
103 bool "sun8i (Allwinner A83T)"
105 select SUNXI_GEN_SUN6I
109 bool "sun8i (Allwinner H3)"
111 select CPU_V7_HAS_NONSEC
112 select CPU_V7_HAS_VIRT
113 select ARCH_SUPPORT_PSCI
114 select SUNXI_GEN_SUN6I
116 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
119 bool "sun9i (Allwinner A80)"
121 select SUNXI_GEN_SUN6I
125 bool "sun50i (Allwinner A64)"
127 select SUNXI_GEN_SUN6I
131 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
134 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
137 int "sunxi dram type"
138 depends on MACH_SUN8I_A83T
141 Set the dram type, 3: DDR3, 7: LPDDR3
144 int "sunxi dram clock speed"
145 default 792 if MACH_SUN9I
146 default 312 if MACH_SUN6I || MACH_SUN8I
147 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
149 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
150 must be a multiple of 24. For the sun9i (A80), the tested values
151 (for DDR3-1600) are 312 to 792.
153 if MACH_SUN5I || MACH_SUN7I
155 int "sunxi mbus clock speed"
158 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
163 int "sunxi dram zq value"
164 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
165 default 127 if MACH_SUN7I
167 Set the dram zq value.
170 bool "sunxi dram odt enable"
171 default n if !MACH_SUN8I_A23
172 default y if MACH_SUN8I_A23
174 Select this to enable dram odt (on die termination).
176 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
178 int "sunxi dram emr1 value"
179 default 0 if MACH_SUN4I
180 default 4 if MACH_SUN5I || MACH_SUN7I
182 Set the dram controller emr1 value.
185 hex "sunxi dram tpr3 value"
188 Set the dram controller tpr3 parameter. This parameter configures
189 the delay on the command lane and also phase shifts, which are
190 applied for sampling incoming read data. The default value 0
191 means that no phase/delay adjustments are necessary. Properly
192 configuring this parameter increases reliability at high DRAM
195 config DRAM_DQS_GATING_DELAY
196 hex "sunxi dram dqs_gating_delay value"
199 Set the dram controller dqs_gating_delay parmeter. Each byte
200 encodes the DQS gating delay for each byte lane. The delay
201 granularity is 1/4 cycle. For example, the value 0x05060606
202 means that the delay is 5 quarter-cycles for one lane (1.25
203 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
204 The default value 0 means autodetection. The results of hardware
205 autodetection are not very reliable and depend on the chip
206 temperature (sometimes producing different results on cold start
207 and warm reboot). But the accuracy of hardware autodetection
208 is usually good enough, unless running at really high DRAM
209 clocks speeds (up to 600MHz). If unsure, keep as 0.
212 prompt "sunxi dram timings"
213 default DRAM_TIMINGS_VENDOR_MAGIC
215 Select the timings of the DDR3 chips.
217 config DRAM_TIMINGS_VENDOR_MAGIC
218 bool "Magic vendor timings from Android"
220 The same DRAM timings as in the Allwinner boot0 bootloader.
222 config DRAM_TIMINGS_DDR3_1066F_1333H
223 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
225 Use the timings of the standard JEDEC DDR3-1066F speed bin for
226 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
227 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
228 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
229 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
230 that down binning to DDR3-1066F is supported (because DDR3-1066F
231 uses a bit faster timings than DDR3-1333H).
233 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
234 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
236 Use the timings of the slowest possible JEDEC speed bin for the
237 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
238 DDR3-800E, DDR3-1066G or DDR3-1333J.
245 config DRAM_ODT_CORRECTION
246 int "sunxi dram odt correction value"
249 Set the dram odt correction value (range -255 - 255). In allwinner
250 fex files, this option is found in bits 8-15 of the u32 odt_en variable
251 in the [dram] section. When bit 31 of the odt_en variable is set
252 then the correction is negative. Usually the value for this is 0.
256 default 816000000 if MACH_SUN50I
257 default 912000000 if MACH_SUN7I
258 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
260 config SYS_CONFIG_NAME
261 default "sun4i" if MACH_SUN4I
262 default "sun5i" if MACH_SUN5I
263 default "sun6i" if MACH_SUN6I
264 default "sun7i" if MACH_SUN7I
265 default "sun8i" if MACH_SUN8I
266 default "sun9i" if MACH_SUN9I
267 default "sun50i" if MACH_SUN50I
276 bool "UART0 on MicroSD breakout board"
279 Repurpose the SD card slot for getting access to the UART0 serial
280 console. Primarily useful only for low level u-boot debugging on
281 tablets, where normal UART0 is difficult to access and requires
282 device disassembly and/or soldering. As the SD card can't be used
283 at the same time, the system can be only booted in the FEL mode.
284 Only enable this if you really know what you are doing.
286 config OLD_SUNXI_KERNEL_COMPAT
287 bool "Enable workarounds for booting old kernels"
290 Set this to enable various workarounds for old kernels, this results in
291 sub-optimal settings for newer kernels, only enable if needed.
294 depends on !UART0_PORT_F
295 default y if ARCH_SUNXI
298 string "Card detect pin for mmc0"
299 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
302 Set the card detect pin for mmc0, leave empty to not use cd. This
303 takes a string in the format understood by sunxi_name_to_gpio, e.g.
304 PH1 for pin 1 of port H.
307 string "Card detect pin for mmc1"
310 See MMC0_CD_PIN help text.
313 string "Card detect pin for mmc2"
316 See MMC0_CD_PIN help text.
319 string "Card detect pin for mmc3"
322 See MMC0_CD_PIN help text.
325 string "Pins for mmc1"
328 Set the pins used for mmc1, when applicable. This takes a string in the
329 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
332 string "Pins for mmc2"
335 See MMC1_PINS help text.
338 string "Pins for mmc3"
341 See MMC1_PINS help text.
343 config MMC_SUNXI_SLOT_EXTRA
344 int "mmc extra slot number"
347 sunxi builds always enable mmc0, some boards also have a second sdcard
348 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
351 config INITIAL_USB_SCAN_DELAY
352 int "delay initial usb scan by x ms to allow builtin devices to init"
355 Some boards have on board usb devices which need longer than the
356 USB spec's 1 second to connect from board powerup. Set this config
357 option to a non 0 value to add an extra delay before the first usb
361 string "Vbus enable pin for usb0 (otg)"
364 Set the Vbus enable pin for usb0 (otg). This takes a string in the
365 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
368 string "Vbus detect pin for usb0 (otg)"
371 Set the Vbus detect pin for usb0 (otg). This takes a string in the
372 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
375 string "ID detect pin for usb0 (otg)"
378 Set the ID detect pin for usb0 (otg). This takes a string in the
379 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
382 string "Vbus enable pin for usb1 (ehci0)"
383 default "PH6" if MACH_SUN4I || MACH_SUN7I
384 default "PH27" if MACH_SUN6I
386 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
387 a string in the format understood by sunxi_name_to_gpio, e.g.
388 PH1 for pin 1 of port H.
391 string "Vbus enable pin for usb2 (ehci1)"
392 default "PH3" if MACH_SUN4I || MACH_SUN7I
393 default "PH24" if MACH_SUN6I
395 See USB1_VBUS_PIN help text.
398 string "Vbus enable pin for usb3 (ehci2)"
401 See USB1_VBUS_PIN help text.
404 bool "Enable I2C/TWI controller 0"
405 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
406 default n if MACH_SUN6I || MACH_SUN8I
409 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
410 its clock and setting up the bus. This is especially useful on devices
411 with slaves connected to the bus or with pins exposed through e.g. an
412 expansion port/header.
415 bool "Enable I2C/TWI controller 1"
419 See I2C0_ENABLE help text.
422 bool "Enable I2C/TWI controller 2"
426 See I2C0_ENABLE help text.
428 if MACH_SUN6I || MACH_SUN7I
430 bool "Enable I2C/TWI controller 3"
434 See I2C0_ENABLE help text.
439 bool "Enable the PRCM I2C/TWI controller"
440 # This is used for the pmic on H3
441 default y if SY8106A_POWER
444 Set this to y to enable the I2C controller which is part of the PRCM.
449 bool "Enable I2C/TWI controller 4"
453 See I2C0_ENABLE help text.
457 bool "Enable support for gpio-s on axp PMICs"
460 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
463 bool "Enable graphical uboot console on HDMI, LCD or VGA"
464 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
467 Say Y here to add support for using a cfb console on the HDMI, LCD
468 or VGA output found on most sunxi devices. See doc/README.video for
469 info on how to select the video output and mode.
472 bool "HDMI output support"
473 depends on VIDEO && !MACH_SUN8I
476 Say Y here to add support for outputting video over HDMI.
479 bool "VGA output support"
480 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
483 Say Y here to add support for outputting video over VGA.
485 config VIDEO_VGA_VIA_LCD
486 bool "VGA via LCD controller support"
487 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
490 Say Y here to add support for external DACs connected to the parallel
491 LCD interface driving a VGA connector, such as found on the
494 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
495 bool "Force sync active high for VGA via LCD controller support"
496 depends on VIDEO_VGA_VIA_LCD
499 Say Y here if you've a board which uses opendrain drivers for the vga
500 hsync and vsync signals. Opendrain drivers cannot generate steep enough
501 positive edges for a stable video output, so on boards with opendrain
502 drivers the sync signals must always be active high.
504 config VIDEO_VGA_EXTERNAL_DAC_EN
505 string "LCD panel power enable pin"
506 depends on VIDEO_VGA_VIA_LCD
509 Set the enable pin for the external VGA DAC. This takes a string in the
510 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
512 config VIDEO_COMPOSITE
513 bool "Composite video output support"
514 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
517 Say Y here to add support for outputting composite video.
519 config VIDEO_LCD_MODE
520 string "LCD panel timing details"
524 LCD panel timing details string, leave empty if there is no LCD panel.
525 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
526 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
527 Also see: http://linux-sunxi.org/LCD
529 config VIDEO_LCD_DCLK_PHASE
530 int "LCD panel display clock phase"
534 Select LCD panel display clock phase shift, range 0-3.
536 config VIDEO_LCD_POWER
537 string "LCD panel power enable pin"
541 Set the power enable pin for the LCD panel. This takes a string in the
542 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
544 config VIDEO_LCD_RESET
545 string "LCD panel reset pin"
549 Set the reset pin for the LCD panel. This takes a string in the format
550 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
552 config VIDEO_LCD_BL_EN
553 string "LCD panel backlight enable pin"
557 Set the backlight enable pin for the LCD panel. This takes a string in the
558 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
561 config VIDEO_LCD_BL_PWM
562 string "LCD panel backlight pwm pin"
566 Set the backlight pwm pin for the LCD panel. This takes a string in the
567 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
569 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
570 bool "LCD panel backlight pwm is inverted"
574 Set this if the backlight pwm output is active low.
576 config VIDEO_LCD_PANEL_I2C
577 bool "LCD panel needs to be configured via i2c"
582 Say y here if the LCD panel needs to be configured via i2c. This
583 will add a bitbang i2c controller using gpios to talk to the LCD.
585 config VIDEO_LCD_PANEL_I2C_SDA
586 string "LCD panel i2c interface SDA pin"
587 depends on VIDEO_LCD_PANEL_I2C
590 Set the SDA pin for the LCD i2c interface. This takes a string in the
591 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
593 config VIDEO_LCD_PANEL_I2C_SCL
594 string "LCD panel i2c interface SCL pin"
595 depends on VIDEO_LCD_PANEL_I2C
598 Set the SCL pin for the LCD i2c interface. This takes a string in the
599 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
602 # Note only one of these may be selected at a time! But hidden choices are
603 # not supported by Kconfig
604 config VIDEO_LCD_IF_PARALLEL
607 config VIDEO_LCD_IF_LVDS
612 prompt "LCD panel support"
615 Select which type of LCD panel to support.
617 config VIDEO_LCD_PANEL_PARALLEL
618 bool "Generic parallel interface LCD panel"
619 select VIDEO_LCD_IF_PARALLEL
621 config VIDEO_LCD_PANEL_LVDS
622 bool "Generic lvds interface LCD panel"
623 select VIDEO_LCD_IF_LVDS
625 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
626 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
627 select VIDEO_LCD_SSD2828
628 select VIDEO_LCD_IF_PARALLEL
630 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
632 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
633 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
634 select VIDEO_LCD_ANX9804
635 select VIDEO_LCD_IF_PARALLEL
636 select VIDEO_LCD_PANEL_I2C
638 Select this for eDP LCD panels with 4 lanes running at 1.62G,
639 connected via an ANX9804 bridge chip.
641 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
642 bool "Hitachi tx18d42vm LCD panel"
643 select VIDEO_LCD_HITACHI_TX18D42VM
644 select VIDEO_LCD_IF_LVDS
646 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
648 config VIDEO_LCD_TL059WV5C0
649 bool "tl059wv5c0 LCD panel"
650 select VIDEO_LCD_PANEL_I2C
651 select VIDEO_LCD_IF_PARALLEL
653 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
654 Aigo M60/M608/M606 tablets.
660 int "GMAC Transmit Clock Delay Chain"
663 Set the GMAC Transmit Clock Delay Chain value.
665 config SPL_STACK_R_ADDR
666 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
667 default 0x2fe00000 if MACH_SUN9I