3 # Note only one of these may be selected at a time! But hidden choices are
4 # not supported by Kconfig
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
11 config SUNXI_GEN_SUN6I
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
20 prompt "Sunxi SoC Variant"
24 bool "sun4i (Allwinner A10)"
26 select SUNXI_GEN_SUN4I
30 bool "sun5i (Allwinner A13)"
32 select SUNXI_GEN_SUN4I
36 bool "sun6i (Allwinner A31)"
38 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
40 select SUNXI_GEN_SUN6I
42 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
45 bool "sun7i (Allwinner A20)"
47 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
49 select SUNXI_GEN_SUN4I
51 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
54 bool "sun8i (Allwinner A23)"
56 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
58 select SUNXI_GEN_SUN6I
60 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
63 bool "sun8i (Allwinner A33)"
65 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
67 select SUNXI_GEN_SUN6I
69 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
72 bool "sun9i (Allwinner A80)"
74 select SUNXI_GEN_SUN6I
78 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
81 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
85 int "sunxi dram clock speed"
86 default 312 if MACH_SUN6I || MACH_SUN8I
87 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
89 Set the dram clock speed, valid range 240 - 480, must be a multiple
92 if MACH_SUN5I || MACH_SUN7I
94 int "sunxi mbus clock speed"
97 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
102 int "sunxi dram zq value"
103 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
104 default 127 if MACH_SUN7I
106 Set the dram zq value.
109 bool "sunxi dram odt enable"
110 default n if !MACH_SUN8I_A23
111 default y if MACH_SUN8I_A23
113 Select this to enable dram odt (on die termination).
115 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
117 int "sunxi dram emr1 value"
118 default 0 if MACH_SUN4I
119 default 4 if MACH_SUN5I || MACH_SUN7I
121 Set the dram controller emr1 value.
124 hex "sunxi dram tpr3 value"
127 Set the dram controller tpr3 parameter. This parameter configures
128 the delay on the command lane and also phase shifts, which are
129 applied for sampling incoming read data. The default value 0
130 means that no phase/delay adjustments are necessary. Properly
131 configuring this parameter increases reliability at high DRAM
134 config DRAM_DQS_GATING_DELAY
135 hex "sunxi dram dqs_gating_delay value"
138 Set the dram controller dqs_gating_delay parmeter. Each byte
139 encodes the DQS gating delay for each byte lane. The delay
140 granularity is 1/4 cycle. For example, the value 0x05060606
141 means that the delay is 5 quarter-cycles for one lane (1.25
142 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
143 The default value 0 means autodetection. The results of hardware
144 autodetection are not very reliable and depend on the chip
145 temperature (sometimes producing different results on cold start
146 and warm reboot). But the accuracy of hardware autodetection
147 is usually good enough, unless running at really high DRAM
148 clocks speeds (up to 600MHz). If unsure, keep as 0.
151 prompt "sunxi dram timings"
152 default DRAM_TIMINGS_VENDOR_MAGIC
154 Select the timings of the DDR3 chips.
156 config DRAM_TIMINGS_VENDOR_MAGIC
157 bool "Magic vendor timings from Android"
159 The same DRAM timings as in the Allwinner boot0 bootloader.
161 config DRAM_TIMINGS_DDR3_1066F_1333H
162 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
164 Use the timings of the standard JEDEC DDR3-1066F speed bin for
165 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
166 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
167 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
168 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
169 that down binning to DDR3-1066F is supported (because DDR3-1066F
170 uses a bit faster timings than DDR3-1333H).
172 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
173 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
175 Use the timings of the slowest possible JEDEC speed bin for the
176 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
177 DDR3-800E, DDR3-1066G or DDR3-1333J.
184 config DRAM_ODT_CORRECTION
185 int "sunxi dram odt correction value"
188 Set the dram odt correction value (range -255 - 255). In allwinner
189 fex files, this option is found in bits 8-15 of the u32 odt_en variable
190 in the [dram] section. When bit 31 of the odt_en variable is set
191 then the correction is negative. Usually the value for this is 0.
195 default 912000000 if MACH_SUN7I
196 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
198 config SYS_CONFIG_NAME
199 default "sun4i" if MACH_SUN4I
200 default "sun5i" if MACH_SUN5I
201 default "sun6i" if MACH_SUN6I
202 default "sun7i" if MACH_SUN7I
203 default "sun8i" if MACH_SUN8I
204 default "sun9i" if MACH_SUN9I
213 bool "UART0 on MicroSD breakout board"
216 Repurpose the SD card slot for getting access to the UART0 serial
217 console. Primarily useful only for low level u-boot debugging on
218 tablets, where normal UART0 is difficult to access and requires
219 device disassembly and/or soldering. As the SD card can't be used
220 at the same time, the system can be only booted in the FEL mode.
221 Only enable this if you really know what you are doing.
223 config OLD_SUNXI_KERNEL_COMPAT
224 boolean "Enable workarounds for booting old kernels"
227 Set this to enable various workarounds for old kernels, this results in
228 sub-optimal settings for newer kernels, only enable if needed.
231 string "Card detect pin for mmc0"
234 Set the card detect pin for mmc0, leave empty to not use cd. This
235 takes a string in the format understood by sunxi_name_to_gpio, e.g.
236 PH1 for pin 1 of port H.
239 string "Card detect pin for mmc1"
242 See MMC0_CD_PIN help text.
245 string "Card detect pin for mmc2"
248 See MMC0_CD_PIN help text.
251 string "Card detect pin for mmc3"
254 See MMC0_CD_PIN help text.
257 string "Pins for mmc1"
260 Set the pins used for mmc1, when applicable. This takes a string in the
261 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
264 string "Pins for mmc2"
267 See MMC1_PINS help text.
270 string "Pins for mmc3"
273 See MMC1_PINS help text.
275 config MMC_SUNXI_SLOT_EXTRA
276 int "mmc extra slot number"
279 sunxi builds always enable mmc0, some boards also have a second sdcard
280 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
284 string "Vbus enable pin for usb0 (otg)"
287 Set the Vbus enable pin for usb0 (otg). This takes a string in the
288 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
291 string "Vbus detect pin for usb0 (otg)"
294 Set the Vbus detect pin for usb0 (otg). This takes a string in the
295 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
298 string "ID detect pin for usb0 (otg)"
301 Set the ID detect pin for usb0 (otg). This takes a string in the
302 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
305 string "Vbus enable pin for usb1 (ehci0)"
306 default "PH6" if MACH_SUN4I || MACH_SUN7I
307 default "PH27" if MACH_SUN6I
309 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
310 a string in the format understood by sunxi_name_to_gpio, e.g.
311 PH1 for pin 1 of port H.
314 string "Vbus enable pin for usb2 (ehci1)"
315 default "PH3" if MACH_SUN4I || MACH_SUN7I
316 default "PH24" if MACH_SUN6I
318 See USB1_VBUS_PIN help text.
321 bool "Enable I2C/TWI controller 0"
322 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
323 default n if MACH_SUN6I || MACH_SUN8I
325 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
326 its clock and setting up the bus. This is especially useful on devices
327 with slaves connected to the bus or with pins exposed through e.g. an
328 expansion port/header.
331 bool "Enable I2C/TWI controller 1"
334 See I2C0_ENABLE help text.
337 bool "Enable I2C/TWI controller 2"
340 See I2C0_ENABLE help text.
342 if MACH_SUN6I || MACH_SUN7I
344 bool "Enable I2C/TWI controller 3"
347 See I2C0_ENABLE help text.
352 bool "Enable I2C/TWI controller 4"
355 See I2C0_ENABLE help text.
359 boolean "Enable support for gpio-s on axp PMICs"
362 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
365 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
368 Say Y here to add support for using a cfb console on the HDMI, LCD
369 or VGA output found on most sunxi devices. See doc/README.video for
370 info on how to select the video output and mode.
373 boolean "HDMI output support"
374 depends on VIDEO && !MACH_SUN8I
377 Say Y here to add support for outputting video over HDMI.
380 boolean "VGA output support"
381 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
384 Say Y here to add support for outputting video over VGA.
386 config VIDEO_VGA_VIA_LCD
387 boolean "VGA via LCD controller support"
388 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
391 Say Y here to add support for external DACs connected to the parallel
392 LCD interface driving a VGA connector, such as found on the
395 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
396 boolean "Force sync active high for VGA via LCD controller support"
397 depends on VIDEO_VGA_VIA_LCD
400 Say Y here if you've a board which uses opendrain drivers for the vga
401 hsync and vsync signals. Opendrain drivers cannot generate steep enough
402 positive edges for a stable video output, so on boards with opendrain
403 drivers the sync signals must always be active high.
405 config VIDEO_VGA_EXTERNAL_DAC_EN
406 string "LCD panel power enable pin"
407 depends on VIDEO_VGA_VIA_LCD
410 Set the enable pin for the external VGA DAC. This takes a string in the
411 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
413 config VIDEO_COMPOSITE
414 boolean "Composite video output support"
415 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
418 Say Y here to add support for outputting composite video.
420 config VIDEO_LCD_MODE
421 string "LCD panel timing details"
425 LCD panel timing details string, leave empty if there is no LCD panel.
426 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
427 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
428 Also see: http://linux-sunxi.org/LCD
430 config VIDEO_LCD_DCLK_PHASE
431 int "LCD panel display clock phase"
435 Select LCD panel display clock phase shift, range 0-3.
437 config VIDEO_LCD_POWER
438 string "LCD panel power enable pin"
442 Set the power enable pin for the LCD panel. This takes a string in the
443 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
445 config VIDEO_LCD_RESET
446 string "LCD panel reset pin"
450 Set the reset pin for the LCD panel. This takes a string in the format
451 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
453 config VIDEO_LCD_BL_EN
454 string "LCD panel backlight enable pin"
458 Set the backlight enable pin for the LCD panel. This takes a string in the
459 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
462 config VIDEO_LCD_BL_PWM
463 string "LCD panel backlight pwm pin"
467 Set the backlight pwm pin for the LCD panel. This takes a string in the
468 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
470 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
471 bool "LCD panel backlight pwm is inverted"
475 Set this if the backlight pwm output is active low.
477 config VIDEO_LCD_PANEL_I2C
478 bool "LCD panel needs to be configured via i2c"
482 Say y here if the LCD panel needs to be configured via i2c. This
483 will add a bitbang i2c controller using gpios to talk to the LCD.
485 config VIDEO_LCD_PANEL_I2C_SDA
486 string "LCD panel i2c interface SDA pin"
487 depends on VIDEO_LCD_PANEL_I2C
490 Set the SDA pin for the LCD i2c interface. This takes a string in the
491 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
493 config VIDEO_LCD_PANEL_I2C_SCL
494 string "LCD panel i2c interface SCL pin"
495 depends on VIDEO_LCD_PANEL_I2C
498 Set the SCL pin for the LCD i2c interface. This takes a string in the
499 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
502 # Note only one of these may be selected at a time! But hidden choices are
503 # not supported by Kconfig
504 config VIDEO_LCD_IF_PARALLEL
507 config VIDEO_LCD_IF_LVDS
512 prompt "LCD panel support"
515 Select which type of LCD panel to support.
517 config VIDEO_LCD_PANEL_PARALLEL
518 bool "Generic parallel interface LCD panel"
519 select VIDEO_LCD_IF_PARALLEL
521 config VIDEO_LCD_PANEL_LVDS
522 bool "Generic lvds interface LCD panel"
523 select VIDEO_LCD_IF_LVDS
525 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
526 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
527 select VIDEO_LCD_SSD2828
528 select VIDEO_LCD_IF_PARALLEL
530 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
532 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
533 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
534 select VIDEO_LCD_ANX9804
535 select VIDEO_LCD_IF_PARALLEL
536 select VIDEO_LCD_PANEL_I2C
538 Select this for eDP LCD panels with 4 lanes running at 1.62G,
539 connected via an ANX9804 bridge chip.
541 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
542 bool "Hitachi tx18d42vm LCD panel"
543 select VIDEO_LCD_HITACHI_TX18D42VM
544 select VIDEO_LCD_IF_LVDS
546 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
548 config VIDEO_LCD_TL059WV5C0
549 bool "tl059wv5c0 LCD panel"
550 select VIDEO_LCD_PANEL_I2C
551 select VIDEO_LCD_IF_PARALLEL
553 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
554 Aigo M60/M608/M606 tablets.
560 int "GMAC Transmit Clock Delay Chain"
563 Set the GMAC Transmit Clock Delay Chain value.