3 # Note only one of these may be selected at a time! But hidden choices are
4 # not supported by Kconfig
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
11 config SUNXI_GEN_SUN6I
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
20 prompt "Sunxi SoC Variant"
24 bool "sun4i (Allwinner A10)"
26 select SUNXI_GEN_SUN4I
30 bool "sun5i (Allwinner A13)"
32 select SUNXI_GEN_SUN4I
36 bool "sun6i (Allwinner A31)"
38 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
40 select SUNXI_GEN_SUN6I
42 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
45 bool "sun7i (Allwinner A20)"
47 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
49 select SUNXI_GEN_SUN4I
51 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
54 bool "sun8i (Allwinner A23)"
56 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
58 select SUNXI_GEN_SUN6I
60 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
63 bool "sun8i (Allwinner A33)"
65 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
67 select SUNXI_GEN_SUN6I
69 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
72 bool "sun8i (Allwinner H3)"
74 select CPU_V7_HAS_NONSEC
75 select CPU_V7_HAS_VIRT
76 select SUNXI_GEN_SUN6I
78 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
80 config MACH_SUN8I_A83T
81 bool "sun8i (Allwinner A83T)"
83 select SUNXI_GEN_SUN6I
87 bool "sun9i (Allwinner A80)"
89 select SUNXI_GEN_SUN6I
93 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
96 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
100 int "sunxi dram clock speed"
101 default 312 if MACH_SUN6I || MACH_SUN8I
102 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
104 Set the dram clock speed, valid range 240 - 480, must be a multiple
107 if MACH_SUN5I || MACH_SUN7I
109 int "sunxi mbus clock speed"
112 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
117 int "sunxi dram zq value"
118 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
119 default 127 if MACH_SUN7I
121 Set the dram zq value.
124 bool "sunxi dram odt enable"
125 default n if !MACH_SUN8I_A23
126 default y if MACH_SUN8I_A23
128 Select this to enable dram odt (on die termination).
130 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
132 int "sunxi dram emr1 value"
133 default 0 if MACH_SUN4I
134 default 4 if MACH_SUN5I || MACH_SUN7I
136 Set the dram controller emr1 value.
139 hex "sunxi dram tpr3 value"
142 Set the dram controller tpr3 parameter. This parameter configures
143 the delay on the command lane and also phase shifts, which are
144 applied for sampling incoming read data. The default value 0
145 means that no phase/delay adjustments are necessary. Properly
146 configuring this parameter increases reliability at high DRAM
149 config DRAM_DQS_GATING_DELAY
150 hex "sunxi dram dqs_gating_delay value"
153 Set the dram controller dqs_gating_delay parmeter. Each byte
154 encodes the DQS gating delay for each byte lane. The delay
155 granularity is 1/4 cycle. For example, the value 0x05060606
156 means that the delay is 5 quarter-cycles for one lane (1.25
157 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
158 The default value 0 means autodetection. The results of hardware
159 autodetection are not very reliable and depend on the chip
160 temperature (sometimes producing different results on cold start
161 and warm reboot). But the accuracy of hardware autodetection
162 is usually good enough, unless running at really high DRAM
163 clocks speeds (up to 600MHz). If unsure, keep as 0.
166 prompt "sunxi dram timings"
167 default DRAM_TIMINGS_VENDOR_MAGIC
169 Select the timings of the DDR3 chips.
171 config DRAM_TIMINGS_VENDOR_MAGIC
172 bool "Magic vendor timings from Android"
174 The same DRAM timings as in the Allwinner boot0 bootloader.
176 config DRAM_TIMINGS_DDR3_1066F_1333H
177 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
179 Use the timings of the standard JEDEC DDR3-1066F speed bin for
180 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
181 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
182 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
183 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
184 that down binning to DDR3-1066F is supported (because DDR3-1066F
185 uses a bit faster timings than DDR3-1333H).
187 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
188 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
190 Use the timings of the slowest possible JEDEC speed bin for the
191 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
192 DDR3-800E, DDR3-1066G or DDR3-1333J.
199 config DRAM_ODT_CORRECTION
200 int "sunxi dram odt correction value"
203 Set the dram odt correction value (range -255 - 255). In allwinner
204 fex files, this option is found in bits 8-15 of the u32 odt_en variable
205 in the [dram] section. When bit 31 of the odt_en variable is set
206 then the correction is negative. Usually the value for this is 0.
210 default 912000000 if MACH_SUN7I
211 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
213 config SYS_CONFIG_NAME
214 default "sun4i" if MACH_SUN4I
215 default "sun5i" if MACH_SUN5I
216 default "sun6i" if MACH_SUN6I
217 default "sun7i" if MACH_SUN7I
218 default "sun8i" if MACH_SUN8I
219 default "sun9i" if MACH_SUN9I
228 bool "UART0 on MicroSD breakout board"
231 Repurpose the SD card slot for getting access to the UART0 serial
232 console. Primarily useful only for low level u-boot debugging on
233 tablets, where normal UART0 is difficult to access and requires
234 device disassembly and/or soldering. As the SD card can't be used
235 at the same time, the system can be only booted in the FEL mode.
236 Only enable this if you really know what you are doing.
238 config OLD_SUNXI_KERNEL_COMPAT
239 boolean "Enable workarounds for booting old kernels"
242 Set this to enable various workarounds for old kernels, this results in
243 sub-optimal settings for newer kernels, only enable if needed.
246 depends on !UART0_PORT_F
247 default y if ARCH_SUNXI
250 string "Card detect pin for mmc0"
253 Set the card detect pin for mmc0, leave empty to not use cd. This
254 takes a string in the format understood by sunxi_name_to_gpio, e.g.
255 PH1 for pin 1 of port H.
258 string "Card detect pin for mmc1"
261 See MMC0_CD_PIN help text.
264 string "Card detect pin for mmc2"
267 See MMC0_CD_PIN help text.
270 string "Card detect pin for mmc3"
273 See MMC0_CD_PIN help text.
276 string "Pins for mmc1"
279 Set the pins used for mmc1, when applicable. This takes a string in the
280 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
283 string "Pins for mmc2"
286 See MMC1_PINS help text.
289 string "Pins for mmc3"
292 See MMC1_PINS help text.
294 config MMC_SUNXI_SLOT_EXTRA
295 int "mmc extra slot number"
298 sunxi builds always enable mmc0, some boards also have a second sdcard
299 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
303 string "Vbus enable pin for usb0 (otg)"
306 Set the Vbus enable pin for usb0 (otg). This takes a string in the
307 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
310 string "Vbus detect pin for usb0 (otg)"
313 Set the Vbus detect pin for usb0 (otg). This takes a string in the
314 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
317 string "ID detect pin for usb0 (otg)"
320 Set the ID detect pin for usb0 (otg). This takes a string in the
321 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
324 string "Vbus enable pin for usb1 (ehci0)"
325 default "PH6" if MACH_SUN4I || MACH_SUN7I
326 default "PH27" if MACH_SUN6I
328 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
329 a string in the format understood by sunxi_name_to_gpio, e.g.
330 PH1 for pin 1 of port H.
333 string "Vbus enable pin for usb2 (ehci1)"
334 default "PH3" if MACH_SUN4I || MACH_SUN7I
335 default "PH24" if MACH_SUN6I
337 See USB1_VBUS_PIN help text.
340 bool "Enable I2C/TWI controller 0"
341 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
342 default n if MACH_SUN6I || MACH_SUN8I
344 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
345 its clock and setting up the bus. This is especially useful on devices
346 with slaves connected to the bus or with pins exposed through e.g. an
347 expansion port/header.
350 bool "Enable I2C/TWI controller 1"
353 See I2C0_ENABLE help text.
356 bool "Enable I2C/TWI controller 2"
359 See I2C0_ENABLE help text.
361 if MACH_SUN6I || MACH_SUN7I
363 bool "Enable I2C/TWI controller 3"
366 See I2C0_ENABLE help text.
370 bool "Enable the PRCM I2C/TWI controller"
373 Set this to y to enable the I2C controller which is part of the PRCM.
377 bool "Enable I2C/TWI controller 4"
380 See I2C0_ENABLE help text.
384 boolean "Enable support for gpio-s on axp PMICs"
387 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
390 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
391 depends on !MACH_SUN8I_A83T
394 Say Y here to add support for using a cfb console on the HDMI, LCD
395 or VGA output found on most sunxi devices. See doc/README.video for
396 info on how to select the video output and mode.
399 boolean "HDMI output support"
400 depends on VIDEO && !MACH_SUN8I
403 Say Y here to add support for outputting video over HDMI.
406 boolean "VGA output support"
407 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
410 Say Y here to add support for outputting video over VGA.
412 config VIDEO_VGA_VIA_LCD
413 boolean "VGA via LCD controller support"
414 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
417 Say Y here to add support for external DACs connected to the parallel
418 LCD interface driving a VGA connector, such as found on the
421 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
422 boolean "Force sync active high for VGA via LCD controller support"
423 depends on VIDEO_VGA_VIA_LCD
426 Say Y here if you've a board which uses opendrain drivers for the vga
427 hsync and vsync signals. Opendrain drivers cannot generate steep enough
428 positive edges for a stable video output, so on boards with opendrain
429 drivers the sync signals must always be active high.
431 config VIDEO_VGA_EXTERNAL_DAC_EN
432 string "LCD panel power enable pin"
433 depends on VIDEO_VGA_VIA_LCD
436 Set the enable pin for the external VGA DAC. This takes a string in the
437 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
439 config VIDEO_COMPOSITE
440 boolean "Composite video output support"
441 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
444 Say Y here to add support for outputting composite video.
446 config VIDEO_LCD_MODE
447 string "LCD panel timing details"
451 LCD panel timing details string, leave empty if there is no LCD panel.
452 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
453 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
454 Also see: http://linux-sunxi.org/LCD
456 config VIDEO_LCD_DCLK_PHASE
457 int "LCD panel display clock phase"
461 Select LCD panel display clock phase shift, range 0-3.
463 config VIDEO_LCD_POWER
464 string "LCD panel power enable pin"
468 Set the power enable pin for the LCD panel. This takes a string in the
469 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
471 config VIDEO_LCD_RESET
472 string "LCD panel reset pin"
476 Set the reset pin for the LCD panel. This takes a string in the format
477 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
479 config VIDEO_LCD_BL_EN
480 string "LCD panel backlight enable pin"
484 Set the backlight enable pin for the LCD panel. This takes a string in the
485 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
488 config VIDEO_LCD_BL_PWM
489 string "LCD panel backlight pwm pin"
493 Set the backlight pwm pin for the LCD panel. This takes a string in the
494 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
496 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
497 bool "LCD panel backlight pwm is inverted"
501 Set this if the backlight pwm output is active low.
503 config VIDEO_LCD_PANEL_I2C
504 bool "LCD panel needs to be configured via i2c"
508 Say y here if the LCD panel needs to be configured via i2c. This
509 will add a bitbang i2c controller using gpios to talk to the LCD.
511 config VIDEO_LCD_PANEL_I2C_SDA
512 string "LCD panel i2c interface SDA pin"
513 depends on VIDEO_LCD_PANEL_I2C
516 Set the SDA pin for the LCD i2c interface. This takes a string in the
517 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
519 config VIDEO_LCD_PANEL_I2C_SCL
520 string "LCD panel i2c interface SCL pin"
521 depends on VIDEO_LCD_PANEL_I2C
524 Set the SCL pin for the LCD i2c interface. This takes a string in the
525 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
528 # Note only one of these may be selected at a time! But hidden choices are
529 # not supported by Kconfig
530 config VIDEO_LCD_IF_PARALLEL
533 config VIDEO_LCD_IF_LVDS
538 prompt "LCD panel support"
541 Select which type of LCD panel to support.
543 config VIDEO_LCD_PANEL_PARALLEL
544 bool "Generic parallel interface LCD panel"
545 select VIDEO_LCD_IF_PARALLEL
547 config VIDEO_LCD_PANEL_LVDS
548 bool "Generic lvds interface LCD panel"
549 select VIDEO_LCD_IF_LVDS
551 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
552 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
553 select VIDEO_LCD_SSD2828
554 select VIDEO_LCD_IF_PARALLEL
556 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
558 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
559 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
560 select VIDEO_LCD_ANX9804
561 select VIDEO_LCD_IF_PARALLEL
562 select VIDEO_LCD_PANEL_I2C
564 Select this for eDP LCD panels with 4 lanes running at 1.62G,
565 connected via an ANX9804 bridge chip.
567 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
568 bool "Hitachi tx18d42vm LCD panel"
569 select VIDEO_LCD_HITACHI_TX18D42VM
570 select VIDEO_LCD_IF_LVDS
572 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
574 config VIDEO_LCD_TL059WV5C0
575 bool "tl059wv5c0 LCD panel"
576 select VIDEO_LCD_PANEL_I2C
577 select VIDEO_LCD_IF_PARALLEL
579 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
580 Aigo M60/M608/M606 tablets.
586 int "GMAC Transmit Clock Delay Chain"
589 Set the GMAC Transmit Clock Delay Chain value.
591 config SPL_STACK_R_ADDR
592 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I
593 default 0x2fe00000 if MACH_SUN9I