3 # Note only one of these may be selected at a time! But hidden choices are
4 # not supported by Kconfig
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
11 config SUNXI_GEN_SUN6I
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
20 prompt "Sunxi SoC Variant"
24 bool "sun4i (Allwinner A10)"
26 select SUNXI_GEN_SUN4I
30 bool "sun5i (Allwinner A13)"
32 select SUNXI_GEN_SUN4I
36 bool "sun6i (Allwinner A31)"
38 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
40 select SUNXI_GEN_SUN6I
42 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
45 bool "sun7i (Allwinner A20)"
47 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
49 select SUNXI_GEN_SUN4I
51 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
54 bool "sun8i (Allwinner A23)"
56 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
58 select SUNXI_GEN_SUN6I
60 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
63 bool "sun8i (Allwinner A33)"
65 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
67 select SUNXI_GEN_SUN6I
69 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
72 bool "sun8i (Allwinner H3)"
74 select CPU_V7_HAS_NONSEC
75 select CPU_V7_HAS_VIRT
76 select SUNXI_GEN_SUN6I
78 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
80 config MACH_SUN8I_A83T
81 bool "sun8i (Allwinner A83T)"
83 select SUNXI_GEN_SUN6I
87 bool "sun9i (Allwinner A80)"
89 select SUNXI_GEN_SUN6I
93 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
96 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
100 depends on MACH_SUN8I_A83T
103 Set the dram type, 3: DDR3, 7: LPDDR3
106 int "sunxi dram clock speed"
107 default 312 if MACH_SUN6I || MACH_SUN8I
108 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
110 Set the dram clock speed, valid range 240 - 480, must be a multiple
113 if MACH_SUN5I || MACH_SUN7I
115 int "sunxi mbus clock speed"
118 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
123 int "sunxi dram zq value"
124 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
125 default 127 if MACH_SUN7I
127 Set the dram zq value.
130 bool "sunxi dram odt enable"
131 default n if !MACH_SUN8I_A23
132 default y if MACH_SUN8I_A23
134 Select this to enable dram odt (on die termination).
136 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
138 int "sunxi dram emr1 value"
139 default 0 if MACH_SUN4I
140 default 4 if MACH_SUN5I || MACH_SUN7I
142 Set the dram controller emr1 value.
145 hex "sunxi dram tpr3 value"
148 Set the dram controller tpr3 parameter. This parameter configures
149 the delay on the command lane and also phase shifts, which are
150 applied for sampling incoming read data. The default value 0
151 means that no phase/delay adjustments are necessary. Properly
152 configuring this parameter increases reliability at high DRAM
155 config DRAM_DQS_GATING_DELAY
156 hex "sunxi dram dqs_gating_delay value"
159 Set the dram controller dqs_gating_delay parmeter. Each byte
160 encodes the DQS gating delay for each byte lane. The delay
161 granularity is 1/4 cycle. For example, the value 0x05060606
162 means that the delay is 5 quarter-cycles for one lane (1.25
163 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
164 The default value 0 means autodetection. The results of hardware
165 autodetection are not very reliable and depend on the chip
166 temperature (sometimes producing different results on cold start
167 and warm reboot). But the accuracy of hardware autodetection
168 is usually good enough, unless running at really high DRAM
169 clocks speeds (up to 600MHz). If unsure, keep as 0.
172 prompt "sunxi dram timings"
173 default DRAM_TIMINGS_VENDOR_MAGIC
175 Select the timings of the DDR3 chips.
177 config DRAM_TIMINGS_VENDOR_MAGIC
178 bool "Magic vendor timings from Android"
180 The same DRAM timings as in the Allwinner boot0 bootloader.
182 config DRAM_TIMINGS_DDR3_1066F_1333H
183 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
185 Use the timings of the standard JEDEC DDR3-1066F speed bin for
186 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
187 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
188 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
189 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
190 that down binning to DDR3-1066F is supported (because DDR3-1066F
191 uses a bit faster timings than DDR3-1333H).
193 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
194 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
196 Use the timings of the slowest possible JEDEC speed bin for the
197 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
198 DDR3-800E, DDR3-1066G or DDR3-1333J.
205 config DRAM_ODT_CORRECTION
206 int "sunxi dram odt correction value"
209 Set the dram odt correction value (range -255 - 255). In allwinner
210 fex files, this option is found in bits 8-15 of the u32 odt_en variable
211 in the [dram] section. When bit 31 of the odt_en variable is set
212 then the correction is negative. Usually the value for this is 0.
216 default 912000000 if MACH_SUN7I
217 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
219 config SYS_CONFIG_NAME
220 default "sun4i" if MACH_SUN4I
221 default "sun5i" if MACH_SUN5I
222 default "sun6i" if MACH_SUN6I
223 default "sun7i" if MACH_SUN7I
224 default "sun8i" if MACH_SUN8I
225 default "sun9i" if MACH_SUN9I
234 bool "UART0 on MicroSD breakout board"
237 Repurpose the SD card slot for getting access to the UART0 serial
238 console. Primarily useful only for low level u-boot debugging on
239 tablets, where normal UART0 is difficult to access and requires
240 device disassembly and/or soldering. As the SD card can't be used
241 at the same time, the system can be only booted in the FEL mode.
242 Only enable this if you really know what you are doing.
244 config OLD_SUNXI_KERNEL_COMPAT
245 boolean "Enable workarounds for booting old kernels"
248 Set this to enable various workarounds for old kernels, this results in
249 sub-optimal settings for newer kernels, only enable if needed.
252 depends on !UART0_PORT_F
253 default y if ARCH_SUNXI
256 string "Card detect pin for mmc0"
259 Set the card detect pin for mmc0, leave empty to not use cd. This
260 takes a string in the format understood by sunxi_name_to_gpio, e.g.
261 PH1 for pin 1 of port H.
264 string "Card detect pin for mmc1"
267 See MMC0_CD_PIN help text.
270 string "Card detect pin for mmc2"
273 See MMC0_CD_PIN help text.
276 string "Card detect pin for mmc3"
279 See MMC0_CD_PIN help text.
282 string "Pins for mmc1"
285 Set the pins used for mmc1, when applicable. This takes a string in the
286 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
289 string "Pins for mmc2"
292 See MMC1_PINS help text.
295 string "Pins for mmc3"
298 See MMC1_PINS help text.
300 config MMC_SUNXI_SLOT_EXTRA
301 int "mmc extra slot number"
304 sunxi builds always enable mmc0, some boards also have a second sdcard
305 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
309 string "Vbus enable pin for usb0 (otg)"
312 Set the Vbus enable pin for usb0 (otg). This takes a string in the
313 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
316 string "Vbus detect pin for usb0 (otg)"
319 Set the Vbus detect pin for usb0 (otg). This takes a string in the
320 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
323 string "ID detect pin for usb0 (otg)"
326 Set the ID detect pin for usb0 (otg). This takes a string in the
327 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
330 string "Vbus enable pin for usb1 (ehci0)"
331 default "PH6" if MACH_SUN4I || MACH_SUN7I
332 default "PH27" if MACH_SUN6I
334 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
335 a string in the format understood by sunxi_name_to_gpio, e.g.
336 PH1 for pin 1 of port H.
339 string "Vbus enable pin for usb2 (ehci1)"
340 default "PH3" if MACH_SUN4I || MACH_SUN7I
341 default "PH24" if MACH_SUN6I
343 See USB1_VBUS_PIN help text.
346 bool "Enable I2C/TWI controller 0"
347 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
348 default n if MACH_SUN6I || MACH_SUN8I
350 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
351 its clock and setting up the bus. This is especially useful on devices
352 with slaves connected to the bus or with pins exposed through e.g. an
353 expansion port/header.
356 bool "Enable I2C/TWI controller 1"
359 See I2C0_ENABLE help text.
362 bool "Enable I2C/TWI controller 2"
365 See I2C0_ENABLE help text.
367 if MACH_SUN6I || MACH_SUN7I
369 bool "Enable I2C/TWI controller 3"
372 See I2C0_ENABLE help text.
377 bool "Enable the PRCM I2C/TWI controller"
378 # This is used for the pmic on H3
379 default y if SY8106A_POWER
381 Set this to y to enable the I2C controller which is part of the PRCM.
386 bool "Enable I2C/TWI controller 4"
389 See I2C0_ENABLE help text.
393 boolean "Enable support for gpio-s on axp PMICs"
396 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
399 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
400 depends on !MACH_SUN8I_A83T
403 Say Y here to add support for using a cfb console on the HDMI, LCD
404 or VGA output found on most sunxi devices. See doc/README.video for
405 info on how to select the video output and mode.
408 boolean "HDMI output support"
409 depends on VIDEO && !MACH_SUN8I
412 Say Y here to add support for outputting video over HDMI.
415 boolean "VGA output support"
416 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
419 Say Y here to add support for outputting video over VGA.
421 config VIDEO_VGA_VIA_LCD
422 boolean "VGA via LCD controller support"
423 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
426 Say Y here to add support for external DACs connected to the parallel
427 LCD interface driving a VGA connector, such as found on the
430 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
431 boolean "Force sync active high for VGA via LCD controller support"
432 depends on VIDEO_VGA_VIA_LCD
435 Say Y here if you've a board which uses opendrain drivers for the vga
436 hsync and vsync signals. Opendrain drivers cannot generate steep enough
437 positive edges for a stable video output, so on boards with opendrain
438 drivers the sync signals must always be active high.
440 config VIDEO_VGA_EXTERNAL_DAC_EN
441 string "LCD panel power enable pin"
442 depends on VIDEO_VGA_VIA_LCD
445 Set the enable pin for the external VGA DAC. This takes a string in the
446 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
448 config VIDEO_COMPOSITE
449 boolean "Composite video output support"
450 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
453 Say Y here to add support for outputting composite video.
455 config VIDEO_LCD_MODE
456 string "LCD panel timing details"
460 LCD panel timing details string, leave empty if there is no LCD panel.
461 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
462 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
463 Also see: http://linux-sunxi.org/LCD
465 config VIDEO_LCD_DCLK_PHASE
466 int "LCD panel display clock phase"
470 Select LCD panel display clock phase shift, range 0-3.
472 config VIDEO_LCD_POWER
473 string "LCD panel power enable pin"
477 Set the power enable pin for the LCD panel. This takes a string in the
478 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
480 config VIDEO_LCD_RESET
481 string "LCD panel reset pin"
485 Set the reset pin for the LCD panel. This takes a string in the format
486 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
488 config VIDEO_LCD_BL_EN
489 string "LCD panel backlight enable pin"
493 Set the backlight enable pin for the LCD panel. This takes a string in the
494 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
497 config VIDEO_LCD_BL_PWM
498 string "LCD panel backlight pwm pin"
502 Set the backlight pwm pin for the LCD panel. This takes a string in the
503 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
505 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
506 bool "LCD panel backlight pwm is inverted"
510 Set this if the backlight pwm output is active low.
512 config VIDEO_LCD_PANEL_I2C
513 bool "LCD panel needs to be configured via i2c"
517 Say y here if the LCD panel needs to be configured via i2c. This
518 will add a bitbang i2c controller using gpios to talk to the LCD.
520 config VIDEO_LCD_PANEL_I2C_SDA
521 string "LCD panel i2c interface SDA pin"
522 depends on VIDEO_LCD_PANEL_I2C
525 Set the SDA pin for the LCD i2c interface. This takes a string in the
526 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
528 config VIDEO_LCD_PANEL_I2C_SCL
529 string "LCD panel i2c interface SCL pin"
530 depends on VIDEO_LCD_PANEL_I2C
533 Set the SCL pin for the LCD i2c interface. This takes a string in the
534 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
537 # Note only one of these may be selected at a time! But hidden choices are
538 # not supported by Kconfig
539 config VIDEO_LCD_IF_PARALLEL
542 config VIDEO_LCD_IF_LVDS
547 prompt "LCD panel support"
550 Select which type of LCD panel to support.
552 config VIDEO_LCD_PANEL_PARALLEL
553 bool "Generic parallel interface LCD panel"
554 select VIDEO_LCD_IF_PARALLEL
556 config VIDEO_LCD_PANEL_LVDS
557 bool "Generic lvds interface LCD panel"
558 select VIDEO_LCD_IF_LVDS
560 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
561 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
562 select VIDEO_LCD_SSD2828
563 select VIDEO_LCD_IF_PARALLEL
565 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
567 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
568 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
569 select VIDEO_LCD_ANX9804
570 select VIDEO_LCD_IF_PARALLEL
571 select VIDEO_LCD_PANEL_I2C
573 Select this for eDP LCD panels with 4 lanes running at 1.62G,
574 connected via an ANX9804 bridge chip.
576 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
577 bool "Hitachi tx18d42vm LCD panel"
578 select VIDEO_LCD_HITACHI_TX18D42VM
579 select VIDEO_LCD_IF_LVDS
581 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
583 config VIDEO_LCD_TL059WV5C0
584 bool "tl059wv5c0 LCD panel"
585 select VIDEO_LCD_PANEL_I2C
586 select VIDEO_LCD_IF_PARALLEL
588 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
589 Aigo M60/M608/M606 tablets.
595 int "GMAC Transmit Clock Delay Chain"
598 Set the GMAC Transmit Clock Delay Chain value.
600 config SPL_STACK_R_ADDR
601 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I
602 default 0x2fe00000 if MACH_SUN9I