board/stxgp3/init.S

   1 /*
   2  * Copyright (C) 2003 Embedded Edge, LLC
   3  * Dan Malek <dan@embeddededge.com>
   4  * Copied from ADS85xx.
   5  * Updates for Silicon Tx GP3 8560.  We only support 32-bit flash
   6  * and DDR with SPD EEPROM configuration.
   7  *
   8  * Copyright (C) 2002,2003, Motorola Inc.
   9  * Xianghua Xiao <X.Xiao@motorola.com>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <ppc_asm.tmpl>
  31 #include <ppc_defs.h>
  32 #include <asm/cache.h>
  33 #include <asm/mmu.h>
  34 #include <config.h>
  35 #include <mpc85xx.h>
  36
  37 #define entry_start \
  38         mflr    r1      ;       \
  39         bl      0f      ;
  40
  41 #define entry_end \
  42 0:      mflr    r0      ;       \
  43         mtlr    r1      ;       \
  44         blr             ;
  45
  46 /* TLB1 entries configuration: */
  47
  48         .section        .bootpg, "ax"
  49         .globl  tlb1_entry
  50 tlb1_entry:
  51         entry_start
  52
  53                 /* If RAMBOOT, we are testing and the BDI has set up
  54                  * much of the MMU already.
  55                  * TLB 4,5 SDRAM
  56                  * TLB 15 is default CCSRBAR.
  57                  */
  58         .long 0x09      /* the following data table uses a few of 16 TLB entries */
  59
  60         .long TLB1_MAS0(1,1,0)
  61         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
  62         .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  63         .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  64
  65         .long TLB1_MAS0(1,2,0)
  66         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
  67         .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  68         .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  69
  70         .long TLB1_MAS0(1,3,0)
  71         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
  72         .long TLB1_MAS2(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  73         .long TLB1_MAS3(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  74         .long TLB1_MAS0(1,4,0)
  75         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
  76         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
  77         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  78
  79         .long TLB1_MAS0(1,5,0)
  80         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
  81         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
  82         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  83
  84         .long TLB1_MAS0(1,6,0)
  85         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
  86 #if defined(CONFIG_RAM_AS_FLASH)
  87         .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  88 #else
  89         .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
  90 #endif
  91         .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  92
  93         .long TLB1_MAS0(1,7,0)
  94         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
  95 #ifdef CONFIG_L2_INIT_RAM
  96         .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
  97 #else
  98         .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
  99 #endif
 100         .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 101
 102         .long TLB1_MAS0(1,8,0)
 103         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
 104         .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 105         .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 106
 107 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
 108         .long TLB1_MAS0(1,15,0)
 109         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
 110         .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 111         .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 112 #else
 113         .long TLB1_MAS0(1,15,0)
 114         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
 115         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
 116         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
 117 #endif
 118         entry_end
 119
 120 /* LAW(Local Access Window) configuration:
 121  * 0000_0000-8000_0000: Up to 2G DDR
 122  * f000_0000-f3ff_ffff: PCI(256M)
 123  * f400_0000-f7ff_ffff: RapidIO(128M)
 124  * f800_0000-ffff_ffff: localbus(128M)
 125  *   f800_0000-fbff_ffff: LBC SDRAM(64M)
 126  *   fc00_0000-fcff_ffff: LBC BCSR (1M, Chip select 1)
 127  *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
 128  *   ff00_0000-ffff_ffff: Flash(16M)
 129  * We don't need a local window for CCSRBAR and flash because they
 130  * reside in their default mapped spaces.
 131  */
 132
 133 #define LAWBAR0 0
 134 #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_2G)) & ~LAWAR_EN)
 135
 136 #define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
 137 #define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
 138
 139 #if !defined(CONFIG_RAM_AS_FLASH)
 140 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
 141 #define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
 142 #else
 143 #define LAWBAR2 0
 144 #define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 145 #endif
 146
 147         .section .bootpg, "ax"
 148         .globl  law_entry
 149 law_entry:
 150         entry_start
 151         .long 0x03
 152         .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
 153         entry_end