2 * (C) Copyright 2005, Embedded Alley Solutions, Inc.
3 * Dan Malek, <dan@embeddedalley.com>
5 * Updates for Silicon Tx GP3 SSA
7 * (C) Copyright 2003,Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/processor.h>
36 #include <asm/immap_85xx.h>
37 #include <asm/fsl_ddr_sdram.h>
40 #include <spd_sdram.h>
45 * I/O Port configuration table
47 * if conf is 1, then that port pin will be configured at boot time
48 * according to the five values podr/pdir/ppar/psor/pdat for that entry
51 const iop_conf_t iop_conf_tab[4][32] = {
53 /* Port A configuration */
54 { /* conf ppar psor pdir podr pdat */
55 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
56 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
57 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
58 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
59 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
60 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
61 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
62 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
63 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
64 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
65 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
66 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
67 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
68 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
69 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
70 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
71 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
72 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
73 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
74 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
75 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
76 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
77 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
78 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
79 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
80 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
81 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
82 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
83 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
84 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
85 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
86 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
89 /* Port B configuration */
90 { /* conf ppar psor pdir podr pdat */
91 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
92 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
93 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
94 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
95 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
96 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
97 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
98 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
99 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
100 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
101 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
102 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
103 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
104 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
105 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
106 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
107 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
108 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
109 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
110 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
111 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
122 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
126 { /* conf ppar psor pdir podr pdat */
127 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
128 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
129 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
130 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
131 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
132 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
133 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
134 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
135 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
136 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
137 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
138 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
139 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
140 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
141 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
142 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
143 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
144 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
145 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
146 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
147 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
148 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
149 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
150 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
151 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
152 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
153 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
154 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
155 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
156 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
157 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
158 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
162 { /* conf ppar psor pdir podr pdat */
163 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
164 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
165 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
166 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
167 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
168 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
169 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
170 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
171 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
172 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
173 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
174 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
175 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
176 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
177 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
178 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
179 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
180 /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
181 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
182 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
183 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
184 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
185 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
186 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
187 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
188 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
189 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
190 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
191 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
198 static uint64_t next_led_update;
204 volatile uint *blatch;
208 blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
210 /* reset Giga bit Ethernet port if needed here */
213 *blatch &= ~0x000000c0;
218 for (i=0; i<1000; i++)
221 *blatch = 0x000000c1; /* Light one led, too */
224 #if 0 /* This is the port we really want to use for debugging. */
225 /* reset the CPM FEC port */
226 #if (CONFIG_ETHER_INDEX == 2)
227 bcsr->bcsr2 &= ~FETH2_RST;
229 bcsr->bcsr2 |= FETH2_RST;
231 #elif (CONFIG_ETHER_INDEX == 3)
232 bcsr->bcsr3 &= ~FETH3_RST;
234 bcsr->bcsr3 |= FETH3_RST;
237 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
239 miiphy_reset("FCC1", 0x0);
241 /* change PHY address to 0x02 */
242 bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
244 bb_miiphy_write(NULL, 0x02, MII_BMCR,
245 BMCR_ANENABLE | BMCR_ANRESTART);
246 #endif /* CONFIG_MII */
251 board_early_init_f(void)
253 #if defined(CONFIG_PCI)
254 volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
256 pci->peer &= 0xffffffdf; /* disable master abort */
259 /* Why is the phy reset done _after_ the ethernet
260 * initialization in arch/powerpc/lib/board.c?
261 * Do it here so it's done before the TSECs are used.
271 printf ("Board: Silicon Tx GPPP SSA Board\n");
275 /* Blinkin' LEDS for Robert.
278 show_activity(int flag)
280 volatile uint *blatch;
282 if (next_led_update > get_ticks())
285 blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
290 *blatch = (0xc0 | led_bit);
292 next_led_update += (get_tbclk() / 4);
295 #if defined(CONFIG_SYS_DRAM_TEST)
298 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
299 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
302 printf("SDRAM test phase 1:\n");
303 for (p = pstart; p < pend; p++)
306 for (p = pstart; p < pend; p++) {
307 if (*p != 0xaaaaaaaa) {
308 printf ("SDRAM test fails at: %08x\n", (uint) p);
313 printf("SDRAM test phase 2:\n");
314 for (p = pstart; p < pend; p++)
317 for (p = pstart; p < pend; p++) {
318 if (*p != 0x55555555) {
319 printf ("SDRAM test fails at: %08x\n", (uint) p);
324 printf("SDRAM test passed.\n");
329 #if defined(CONFIG_PCI)
332 * Initialize PCI Devices, report devices found.
335 #ifndef CONFIG_PCI_PNP
336 static struct pci_config_table pci_stxgp3_config_table[] = {
337 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
338 PCI_IDSEL_NUMBER, PCI_ANY_ID,
339 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
341 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
348 static struct pci_controller hose[] = {
349 #ifndef CONFIG_PCI_PNP
350 { config_table: pci_stxgp3_config_table,},
354 #ifdef CONFIG_MPC85XX_PCI2
359 #endif /* CONFIG_PCI */
366 extern void pci_mpc85xx_init(struct pci_controller *hose);
368 pci_mpc85xx_init(hose);
369 #endif /* CONFIG_PCI */
372 int board_eth_init(bd_t *bis)
374 cpu_eth_init(bis); /* Initialize TSECs first */
375 return pci_eth_init(bis);