2 * Copyright 2008 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
13 struct fsl_e_tlb_entry tlb_table[] = {
14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
29 * TLB 0: 16M Non-cacheable, guarded
30 * 0xff000000 16M FLASH
31 * Out of reset this entry is only 4K.
33 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
34 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
35 0, 0, BOOKE_PAGESZ_16M, 1),
38 * TLB 1: 256M Non-cacheable, guarded
39 * 0x80000000 256M PCI1 MEM First half
41 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
42 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
43 0, 1, BOOKE_PAGESZ_256M, 1),
46 * TLB 2: 256M Non-cacheable, guarded
47 * 0x90000000 256M PCI1 MEM Second half
49 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51 0, 2, BOOKE_PAGESZ_256M, 1),
54 * TLB 3: 256M Non-cacheable, guarded
55 * 0xc0000000 256M Rapid IO MEM First half
57 SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 0, 3, BOOKE_PAGESZ_256M, 1),
62 * TLB 4: 256M Non-cacheable, guarded
63 * 0xd0000000 256M Rapid IO MEM Second half
65 SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 0, 4, BOOKE_PAGESZ_256M, 1),
70 * TLB 5: 64M Non-cacheable, guarded
71 * 0xe000_0000 1M CCSRBAR
72 * 0xe200_0000 16M PCI1 IO
74 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76 0, 5, BOOKE_PAGESZ_64M, 1),
79 * TLB 6: 64M Cacheable, non-guarded
80 * 0xf000_0000 64M LBC SDRAM
82 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
83 MAS3_SX|MAS3_SW|MAS3_SR, 0,
84 0, 6, BOOKE_PAGESZ_64M, 1),
87 * TLB 7: 16K Non-cacheable, guarded
88 * 0xfc000000 16K Configuration Latch register
90 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE,
91 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92 0, 7, BOOKE_PAGESZ_16K, 1),
94 #if !defined(CONFIG_SPD_EEPROM)
97 * 0x00000000 64M DDR System memory
98 * 0x04000000 64M DDR System memory
99 * Without SPD EEPROM configured DDR, this must be setup manually.
100 * Make sure the TLB count at the top of this table is correct.
101 * Likely it needs to be increased by two for these entries.
103 #error("Update the number of table entries in tlb1_entry")
104 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
105 MAS3_SX|MAS3_SW|MAS3_SR, 0,
106 0, 8, BOOKE_PAGESZ_64M, 1),
108 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
109 MAS3_SX|MAS3_SW|MAS3_SR, 0,
110 0, 9, BOOKE_PAGESZ_64M, 1),
114 int num_tlb_entries = ARRAY_SIZE(tlb_table);