1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
8 #include <asm/arch/regs.h>
9 #include <asm/arch/spl.h>
14 #define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
15 #define JH7110_CLK_CPU_ROOT_SHIFT 24
16 #define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
18 int spl_board_init_f(void)
24 debug("JH7110 SPL init failed: %d\n", ret);
31 u32 spl_boot_device(void)
35 mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
36 & JH7110_BOOT_MODE_SELECT_MASK;
39 return BOOT_DEVICE_SPI;
42 return BOOT_DEVICE_MMC2;
45 return BOOT_DEVICE_MMC1;
48 return BOOT_DEVICE_UART;
51 debug("Unsupported boot device 0x%x.\n", mode);
52 return BOOT_DEVICE_NONE;
56 void board_init_f(ulong dummy)
60 ret = spl_early_init();
62 panic("spl_early_init() failed: %d\n", ret);
64 riscv_cpu_setup(NULL, NULL);
65 preloader_console_init();
67 /* Set the parent clock of cpu_root clock to pll0,
68 * it must be initialized here
70 clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
71 JH7110_CLK_CPU_ROOT_MASK,
72 BIT(JH7110_CLK_CPU_ROOT_SHIFT));
74 ret = spl_board_init_f();
76 debug("spl_board_init_f init failed: %d\n", ret);
81 #if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
82 int board_fit_config_name_match(const char *name)
84 /* boot using first FIT config */