1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
10 #include <generic-phy.h>
14 #include <asm/arch/stm32.h>
16 #include <power/regulator.h>
17 #include <usb/dwc2_udc.h>
20 * Get a global data pointer
22 DECLARE_GLOBAL_DATA_PTR;
24 #define STM32MP_GUSBCFG 0x40002407
26 #define STM32MP_GGPIO 0x38
27 #define STM32MP_GGPIO_VBUS_SENSING BIT(21)
29 static struct dwc2_plat_otg_data stm32mp_otg_data = {
30 .usb_gusbcfg = STM32MP_GUSBCFG,
33 static struct reset_ctl usbotg_reset;
35 int board_usb_init(int index, enum usb_init_type init)
37 struct fdtdec_phandle_args args;
39 const void *blob = gd->fdt_blob;
46 /* find the usb otg node */
47 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
49 debug("Not found usb_otg device\n");
53 if (!fdtdec_get_is_enabled(blob, node)) {
54 debug("stm32 usbotg is disabled in the device tree\n");
59 ret = fdtdec_parse_phandle_with_args(blob, node, "clocks",
60 "#clock-cells", 0, 0, &args);
62 debug("usbotg has no clocks defined in the device tree\n");
66 ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev);
70 if (args.args_count != 1) {
71 debug("Can't find clock ID in the device tree\n");
76 clk.id = args.args[0];
78 ret = clk_enable(&clk);
80 debug("Failed to enable usbotg clock\n");
85 ret = fdtdec_parse_phandle_with_args(blob, node, "resets",
86 "#reset-cells", 0, 0, &args);
88 debug("usbotg has no resets defined in the device tree\n");
92 ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node, &dev);
93 if (ret || args.args_count != 1)
96 usbotg_reset.dev = dev;
97 usbotg_reset.id = args.args[0];
99 reset_assert(&usbotg_reset);
101 reset_deassert(&usbotg_reset);
104 ret = fdtdec_parse_phandle_with_args(blob, node, "phys",
105 "#phy-cells", 0, 0, &args);
107 phy_provider = fdt_parent_offset(blob, args.node);
108 ret = uclass_get_device_by_of_offset(UCLASS_PHY,
114 phy.id = fdtdec_get_uint(blob, args.node, "reg", -1);
116 ret = generic_phy_power_on(&phy);
118 debug("unable to power on the phy\n");
122 ret = generic_phy_init(&phy);
124 debug("failed to init usb phy\n");
129 /* Parse and store data needed for gadget */
130 stm32mp_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
131 if (stm32mp_otg_data.regs_otg == FDT_ADDR_T_NONE) {
132 debug("usbotg: can't get base address\n");
137 stm32mp_otg_data.rx_fifo_sz = fdtdec_get_int(blob, node,
138 "g-rx-fifo-size", 0);
139 stm32mp_otg_data.np_tx_fifo_sz = fdtdec_get_int(blob, node,
140 "g-np-tx-fifo-size", 0);
141 stm32mp_otg_data.tx_fifo_sz = fdtdec_get_int(blob, node,
142 "g-tx-fifo-size", 0);
143 /* Enable voltage level detector */
144 if (!(fdtdec_parse_phandle_with_args(blob, node, "usb33d-supply",
145 NULL, 0, 0, &args))) {
146 if (!uclass_get_device_by_of_offset(UCLASS_REGULATOR,
148 ret = regulator_set_enable(dev, true);
150 debug("Failed to enable usb33d\n");
155 /* Enable vbus sensing */
156 setbits_le32(stm32mp_otg_data.regs_otg + STM32MP_GGPIO,
157 STM32MP_GGPIO_VBUS_SENSING);
159 return dwc2_udc_probe(&stm32mp_otg_data);
162 generic_phy_exit(&phy);
165 generic_phy_power_off(&phy);
173 int board_usb_cleanup(int index, enum usb_init_type init)
176 reset_assert(&usbotg_reset);
178 reset_deassert(&usbotg_reset);
183 int board_late_init(void)
188 /* board dependent setup after realloc */
191 /* address of boot parameters */
192 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
194 if (IS_ENABLED(CONFIG_LED))