1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
9 #include <asm/arch/ddr.h>
10 #include <power/pmic.h>
11 #include <power/stpmu1.h>
13 #ifdef CONFIG_PMIC_STPMU1
14 int board_ddr_power_init(void)
19 ret = uclass_get_device_by_driver(UCLASS_PMIC,
20 DM_GET_DRIVER(pmic_stpmu1), &dev);
22 /* No PMIC on board */
25 /* Set LDO3 to sync mode */
26 ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
30 ret &= ~STPMU1_LDO3_MODE;
31 ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
32 ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
34 ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
39 /* Set BUCK2 to 1.35V */
40 ret = pmic_clrsetbits(dev,
41 STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
42 STPMU1_BUCK_OUTPUT_MASK,
43 STPMU1_BUCK2_1350000V);
47 /* Enable BUCK2 and VREF */
48 ret = pmic_clrsetbits(dev,
49 STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
50 STPMU1_BUCK_EN, STPMU1_BUCK_EN);
54 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
56 ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
57 STPMU1_VREF_EN, STPMU1_VREF_EN);
61 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
64 ret = pmic_clrsetbits(dev,
65 STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
66 STPMU1_LDO_EN, STPMU1_LDO_EN);
70 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);