board/st/stm32mp1/board.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/ddr.h>
  10 #include <power/pmic.h>
  11 #include <power/stpmic1.h>
  12
  13 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  14 void board_debug_uart_init(void)
  15 {
  16 #if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
  17
  18 #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
  19 #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
  20
  21         /* UART4 clock enable */
  22         setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
  23
  24 #define GPIOG_BASE 0x50008000
  25         /* GPIOG clock enable */
  26         writel(BIT(6), RCC_MP_AHB4ENSETR);
  27         /* GPIO configuration for EVAL board
  28          * => Uart4 TX = G11
  29          */
  30         writel(0xffbfffff, GPIOG_BASE + 0x00);
  31         writel(0x00006000, GPIOG_BASE + 0x24);
  32 #else
  33
  34 #error("CONFIG_DEBUG_UART_BASE: not supported value")
  35
  36 #endif
  37 }
  38 #endif
  39
  40 #ifdef CONFIG_PMIC_STPMIC1
  41 int board_ddr_power_init(enum ddr_type ddr_type)
  42 {
  43         struct udevice *dev;
  44         bool buck3_at_1800000v = false;
  45         int ret;
  46
  47         ret = uclass_get_device_by_driver(UCLASS_PMIC,
  48                                           DM_GET_DRIVER(pmic_stpmic1), &dev);
  49         if (ret)
  50                 /* No PMIC on board */
  51                 return 0;
  52
  53         switch (ddr_type) {
  54         case STM32MP_DDR3:
  55                 /* VTT = Set LDO3 to sync mode */
  56                 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
  57                 if (ret < 0)
  58                         return ret;
  59
  60                 ret &= ~STPMIC1_LDO3_MODE;
  61                 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
  62                 ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
  63
  64                 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
  65                                      ret);
  66                 if (ret < 0)
  67                         return ret;
  68
  69                 /* VDD_DDR = Set BUCK2 to 1.35V */
  70                 ret = pmic_clrsetbits(dev,
  71                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
  72                                       STPMIC1_BUCK_VOUT_MASK,
  73                                       STPMIC1_BUCK2_1350000V);
  74                 if (ret < 0)
  75                         return ret;
  76
  77                 /* Enable VDD_DDR = BUCK2 */
  78                 ret = pmic_clrsetbits(dev,
  79                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
  80                                       STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
  81                 if (ret < 0)
  82                         return ret;
  83
  84                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
  85
  86                 /* Enable VREF */
  87                 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
  88                                       STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
  89                 if (ret < 0)
  90                         return ret;
  91
  92                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
  93
  94                 /* Enable VTT = LDO3 */
  95                 ret = pmic_clrsetbits(dev,
  96                                       STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
  97                                       STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
  98                 if (ret < 0)
  99                         return ret;
 100
 101                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 102
 103                 break;
 104
 105         case STM32MP_LPDDR2:
 106         case STM32MP_LPDDR3:
 107                 /*
 108                  * configure VDD_DDR1 = LDO3
 109                  * Set LDO3 to 1.8V
 110                  * + bypass mode if BUCK3 = 1.8V
 111                  * + normal mode if BUCK3 != 1.8V
 112                  */
 113                 ret = pmic_reg_read(dev,
 114                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
 115                 if (ret < 0)
 116                         return ret;
 117
 118                 if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
 119                         buck3_at_1800000v = true;
 120
 121                 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
 122                 if (ret < 0)
 123                         return ret;
 124
 125                 ret &= ~STPMIC1_LDO3_MODE;
 126                 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
 127                 ret |= STPMIC1_LDO3_1800000;
 128                 if (buck3_at_1800000v)
 129                         ret |= STPMIC1_LDO3_MODE;
 130
 131                 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 132                                      ret);
 133                 if (ret < 0)
 134                         return ret;
 135
 136                 /* VDD_DDR2 : Set BUCK2 to 1.2V */
 137                 ret = pmic_clrsetbits(dev,
 138                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
 139                                       STPMIC1_BUCK_VOUT_MASK,
 140                                       STPMIC1_BUCK2_1200000V);
 141                 if (ret < 0)
 142                         return ret;
 143
 144                 /* Enable VDD_DDR1 = LDO3 */
 145                 ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 146                                       STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
 147                 if (ret < 0)
 148                         return ret;
 149
 150                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 151
 152                 /* Enable VDD_DDR2 =BUCK2 */
 153                 ret = pmic_clrsetbits(dev,
 154                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
 155                                       STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
 156                 if (ret < 0)
 157                         return ret;
 158
 159                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 160
 161                 /* Enable VREF */
 162                 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
 163                                       STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
 164                 if (ret < 0)
 165                         return ret;
 166
 167                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 168
 169                 break;
 170
 171         default:
 172                 break;
 173         };
 174
 175         return 0;
 176 }
 177 #endif