3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/armv7m.h>
11 #include <asm/arch/stm32.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/arch/rcc.h>
14 #include <asm/arch/fmc.h>
15 #include <dm/platdata.h>
16 #include <dm/platform_data/serial_stm32x7.h>
17 #include <asm/arch/stm32_periph.h>
18 #include <asm/arch/stm32_defs.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 const struct stm32_gpio_ctl gpio_ctl_gpout = {
23 .mode = STM32_GPIO_MODE_OUT,
24 .otype = STM32_GPIO_OTYPE_PP,
25 .speed = STM32_GPIO_SPEED_50M,
26 .pupd = STM32_GPIO_PUPD_NO,
30 const struct stm32_gpio_ctl gpio_ctl_usart = {
31 .mode = STM32_GPIO_MODE_AF,
32 .otype = STM32_GPIO_OTYPE_PP,
33 .speed = STM32_GPIO_SPEED_50M,
34 .pupd = STM32_GPIO_PUPD_UP,
38 const struct stm32_gpio_ctl gpio_ctl_fmc = {
39 .mode = STM32_GPIO_MODE_AF,
40 .otype = STM32_GPIO_OTYPE_PP,
41 .speed = STM32_GPIO_SPEED_100M,
42 .pupd = STM32_GPIO_PUPD_NO,
46 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
47 /* Chip is LQFP144, see DM00077036.pdf for details */
48 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
49 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
50 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
51 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
52 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
53 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
54 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
55 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
56 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
57 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
58 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
59 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
60 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
61 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
62 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
63 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
65 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
66 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
68 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
69 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
71 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
72 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
73 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
74 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
75 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
76 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
77 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
78 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
79 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
80 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
81 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
82 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
84 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */
85 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
86 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
87 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */
88 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */
90 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
93 static int fmc_setup_gpio(void)
98 clock_setup(GPIO_B_CLOCK_CFG);
99 clock_setup(GPIO_C_CLOCK_CFG);
100 clock_setup(GPIO_D_CLOCK_CFG);
101 clock_setup(GPIO_E_CLOCK_CFG);
102 clock_setup(GPIO_F_CLOCK_CFG);
103 clock_setup(GPIO_G_CLOCK_CFG);
104 clock_setup(GPIO_H_CLOCK_CFG);
106 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
107 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
118 * STM32 RCC FMC specific definitions
120 #define RCC_ENR_FMC (1 << 0) /* FMC module clock */
122 static inline u32 _ns2clk(u32 ns, u32 freq)
124 u32 tmp = freq/1000000;
125 return (tmp * ns) / 1000;
128 #define NS2CLK(ns) (_ns2clk(ns, freq))
131 * Following are timings for IS42S16400J, from corresponding datasheet
133 #define SDRAM_CAS 3 /* 3 cycles */
134 #define SDRAM_NB 1 /* Number of banks */
135 #define SDRAM_MWID 1 /* 16 bit memory */
137 #define SDRAM_NR 0x1 /* 12-bit row */
138 #define SDRAM_NC 0x0 /* 8-bit col */
139 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
140 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
142 #define SDRAM_TRRD NS2CLK(12)
143 #define SDRAM_TRCD NS2CLK(18)
144 #define SDRAM_TRP NS2CLK(18)
145 #define SDRAM_TRAS NS2CLK(42)
146 #define SDRAM_TRC NS2CLK(60)
147 #define SDRAM_TRFC NS2CLK(60)
148 #define SDRAM_TCDL (1 - 1)
149 #define SDRAM_TRDL NS2CLK(12)
150 #define SDRAM_TBDL (1 - 1)
151 #define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
152 #define SDRAM_TCCD (1 - 1)
154 #define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */
155 #define SDRAM_TMRD 1 /* Page 10, Mode Register Set */
158 /* Last data in to row precharge, need also comply ineq on page 1648 */
159 #define SDRAM_TWR max(\
160 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
161 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
165 #define SDRAM_MODE_BL_SHIFT 0
166 #define SDRAM_MODE_CAS_SHIFT 4
167 #define SDRAM_MODE_BL 0
168 #define SDRAM_MODE_CAS SDRAM_CAS
175 rv = fmc_setup_gpio();
179 setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC);
182 * Get frequency for NS2CLK calculation.
184 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
187 CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
188 | SDRAM_CAS << FMC_SDCR_CAS_SHIFT
189 | SDRAM_NB << FMC_SDCR_NB_SHIFT
190 | SDRAM_MWID << FMC_SDCR_MWID_SHIFT
191 | SDRAM_NR << FMC_SDCR_NR_SHIFT
192 | SDRAM_NC << FMC_SDCR_NC_SHIFT
193 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
194 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
195 &STM32_SDRAM_FMC->sdcr1);
198 SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
199 | SDRAM_TRP << FMC_SDTR_TRP_SHIFT
200 | SDRAM_TWR << FMC_SDTR_TWR_SHIFT
201 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT
202 | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
203 | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
204 | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
205 &STM32_SDRAM_FMC->sdtr1);
207 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
208 &STM32_SDRAM_FMC->sdcmr);
210 udelay(200); /* 200 us delay, page 10, "Power-Up" */
213 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
214 &STM32_SDRAM_FMC->sdcmr);
219 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
220 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
225 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
226 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
227 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
228 &STM32_SDRAM_FMC->sdcmr);
234 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
235 &STM32_SDRAM_FMC->sdcmr);
240 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
243 * Fill in global info with description of SRAM configuration
245 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
246 gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
248 gd->ram_size = CONFIG_SYS_RAM_SIZE;
253 static const struct stm32_gpio_dsc usart_gpio[] = {
254 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_6}, /* TX */
255 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_7}, /* RX */
258 int uart_setup_gpio(void)
263 clock_setup(GPIO_C_CLOCK_CFG);
264 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
265 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
274 static const struct stm32x7_serial_platdata serial_platdata = {
275 .base = (struct stm32_usart *)USART6_BASE,
276 .clock = CONFIG_SYS_CLK_FREQ,
279 U_BOOT_DEVICE(stm32x7_serials) = {
280 .name = "serial_stm32x7",
281 .platdata = &serial_platdata,
284 u32 get_board_rev(void)
289 int board_early_init_f(void)
293 res = uart_setup_gpio();
294 clock_setup(USART6_CLOCK_CFG);
303 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;