3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/armv7m.h>
11 #include <asm/arch/stm32.h>
12 #include <asm/arch/gpio.h>
13 #include <dm/platdata.h>
14 #include <dm/platform_data/serial_stm32x7.h>
15 #include <asm/arch/stm32_periph.h>
16 #include <asm/arch/stm32_defs.h>
17 #include <asm/arch/syscfg.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 const struct stm32_gpio_ctl gpio_ctl_gpout = {
22 .mode = STM32_GPIO_MODE_OUT,
23 .otype = STM32_GPIO_OTYPE_PP,
24 .speed = STM32_GPIO_SPEED_50M,
25 .pupd = STM32_GPIO_PUPD_NO,
29 const struct stm32_gpio_ctl gpio_ctl_fmc = {
30 .mode = STM32_GPIO_MODE_AF,
31 .otype = STM32_GPIO_OTYPE_PP,
32 .speed = STM32_GPIO_SPEED_100M,
33 .pupd = STM32_GPIO_PUPD_NO,
37 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
38 /* Chip is LQFP144, see DM00077036.pdf for details */
39 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
40 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
41 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
42 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
43 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
44 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
45 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
46 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
47 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
48 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
49 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
50 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
51 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
52 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
53 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
54 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
56 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
57 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
59 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
60 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
62 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
63 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
64 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
65 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
66 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
67 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
68 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
69 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
70 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
71 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
72 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
73 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
75 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */
76 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
77 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
78 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */
79 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */
81 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
84 static int fmc_setup_gpio(void)
89 clock_setup(GPIO_B_CLOCK_CFG);
90 clock_setup(GPIO_C_CLOCK_CFG);
91 clock_setup(GPIO_D_CLOCK_CFG);
92 clock_setup(GPIO_E_CLOCK_CFG);
93 clock_setup(GPIO_F_CLOCK_CFG);
94 clock_setup(GPIO_G_CLOCK_CFG);
95 clock_setup(GPIO_H_CLOCK_CFG);
97 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
98 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
112 rv = fmc_setup_gpio();
116 clock_setup(FMC_CLOCK_CFG);
120 * Fill in global info with description of SRAM configuration
122 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
123 gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
125 gd->ram_size = CONFIG_SYS_RAM_SIZE;
129 int uart_setup_gpio(void)
131 clock_setup(GPIO_A_CLOCK_CFG);
132 clock_setup(GPIO_B_CLOCK_CFG);
136 #ifdef CONFIG_ETH_DESIGNWARE
138 static int stmmac_setup(void)
140 clock_setup(SYSCFG_CLOCK_CFG);
142 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
144 clock_setup(GPIO_A_CLOCK_CFG);
145 clock_setup(GPIO_C_CLOCK_CFG);
146 clock_setup(GPIO_G_CLOCK_CFG);
147 clock_setup(STMMAC_CLOCK_CFG);
153 #ifdef CONFIG_STM32_QSPI
155 static int qspi_setup(void)
157 clock_setup(GPIO_B_CLOCK_CFG);
158 clock_setup(GPIO_D_CLOCK_CFG);
159 clock_setup(GPIO_E_CLOCK_CFG);
164 u32 get_board_rev(void)
169 int board_early_init_f(void)
173 res = uart_setup_gpio();
177 #ifdef CONFIG_ETH_DESIGNWARE
178 res = stmmac_setup();
183 #ifdef CONFIG_STM32_QSPI
194 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;