2 * (C) Copyright 2011, 2012, 2013
3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
4 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
5 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
6 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
9 * Kamil Lulko, <kamil.lulko@gmail.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <stm32_rcc.h>
18 #include <asm/arch/stm32.h>
19 #include <asm/arch/gpio.h>
20 #include <dm/platform_data/serial_stm32.h>
21 #include <asm/arch/stm32_periph.h>
22 #include <asm/arch/stm32_defs.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 const struct stm32_gpio_ctl gpio_ctl_gpout = {
27 .mode = STM32_GPIO_MODE_OUT,
28 .otype = STM32_GPIO_OTYPE_PP,
29 .speed = STM32_GPIO_SPEED_50M,
30 .pupd = STM32_GPIO_PUPD_NO,
34 const struct stm32_gpio_ctl gpio_ctl_usart = {
35 .mode = STM32_GPIO_MODE_AF,
36 .otype = STM32_GPIO_OTYPE_PP,
37 .speed = STM32_GPIO_SPEED_50M,
38 .pupd = STM32_GPIO_PUPD_UP,
39 .af = STM32_GPIO_USART
42 static const struct stm32_gpio_dsc usart_gpio[] = {
43 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */
44 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */
47 int uart_setup_gpio(void)
52 clock_setup(GPIO_A_CLOCK_CFG);
53 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
54 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
63 const struct stm32_gpio_ctl gpio_ctl_fmc = {
64 .mode = STM32_GPIO_MODE_AF,
65 .otype = STM32_GPIO_OTYPE_PP,
66 .speed = STM32_GPIO_SPEED_100M,
67 .pupd = STM32_GPIO_PUPD_NO,
71 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
72 /* Chip is LQFP144, see DM00077036.pdf for details */
73 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
74 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
75 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
76 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
77 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
78 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
79 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
80 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
81 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
82 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
83 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
84 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
85 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
86 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
87 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
88 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
89 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
90 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
91 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
92 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
93 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
94 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
95 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
96 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
97 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
98 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
99 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
100 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
101 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
102 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
103 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
104 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
105 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */
106 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
107 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
108 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */
109 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */
110 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
113 static int fmc_setup_gpio(void)
118 clock_setup(GPIO_B_CLOCK_CFG);
119 clock_setup(GPIO_C_CLOCK_CFG);
120 clock_setup(GPIO_D_CLOCK_CFG);
121 clock_setup(GPIO_E_CLOCK_CFG);
122 clock_setup(GPIO_F_CLOCK_CFG);
123 clock_setup(GPIO_G_CLOCK_CFG);
125 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
126 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
137 * STM32 RCC FMC specific definitions
139 #define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */
146 rv = fmc_setup_gpio();
150 setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
152 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
154 debug("DRAM init failed: %d\n", rv);
158 if (fdtdec_setup_memory_size() != 0)
164 int dram_init_banksize(void)
166 fdtdec_setup_memory_banksize();
171 static const struct stm32_serial_platdata serial_platdata = {
172 .base = (struct stm32_usart *)STM32_USART1_BASE,
175 U_BOOT_DEVICE(stm32_serials) = {
176 .name = "serial_stm32",
177 .platdata = &serial_platdata,
180 u32 get_board_rev(void)
185 int board_early_init_f(void)
191 res = uart_setup_gpio();
194 clock_setup(USART1_CLOCK_CFG);
201 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
206 #ifdef CONFIG_MISC_INIT_R
207 int misc_init_r(void)
210 uint32_t u_id_low, u_id_mid, u_id_high;
212 if (!env_get("serial#")) {
213 u_id_low = readl(&STM32_U_ID->u_id_low);
214 u_id_mid = readl(&STM32_U_ID->u_id_mid);
215 u_id_high = readl(&STM32_U_ID->u_id_high);
216 sprintf(serialno, "%08x%08x%08x",
217 u_id_high, u_id_mid, u_id_low);
218 env_set("serial#", serialno);