1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
6 /***************************************************************************************************************************/
7 /* VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
8 /* AP x x v v v v v v v v v x v v v v v v v */
9 /* CP0 x x v v v x x x x v x x x x x x x x x */
10 /* CP1 x x v x x x x x x x x x x x x x x x x */
11 /* CP2 x x v v x v x x x v x x x x x x x x x */
12 /* EX0 x x x v x x x x x x x x x x x x x x x */
13 /* EX1 x x x x v x x x x x x x x x x x x x x */
14 /* EX2 x x x v x x x x x x x x x x x x x x x */
15 /***************************************************************************************************************************/
17 /***************************************************************************************************************************/
18 /* CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA LPGEN LPARM LPMEM LPCORE LPBG BG */
19 /* AP v v v v v v v v v v v x v v v v v v */
20 /* CP0 x x x x x x x x x x x x x x x x x x */
21 /* CP1 x x x x x x x x x x x x x x x x x x */
22 /* CP2 x x x x x x v v x x x x x x x x x x */
23 /* EX0 x x x x x x x x v x x x x x x x x x */
24 /* EX1 x x x x x x x x x x x x x x x x x x */
25 /* EX2 x x x x x x x x x x x x x x x x x x */
26 /***************************************************************************************************************************/
28 void init_ldo_sleep_gr(void)
32 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0x6e7f));
35 reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT);
38 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
46 //BIT_LDO_EMMCCORE_PD|
57 reg_val = ANA_REG_GET(ANA_REG_GLB_LDO_PD_CTRL);
58 reg_val |= BIT_DCDC_WPA_PD;
59 ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL, reg_val);
61 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0));
63 /**********************************************
64 * Following is AP LDO A DIE Sleep Control *
65 *********************************************/
66 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
68 //BIT_SLP_DCDCGEN_PD_EN |
69 //BIT_SLP_DCDCWPA_PD_EN |
70 BIT_SLP_DCDCARM_PD_EN |
71 BIT_SLP_LDORF0_PD_EN |
72 BIT_SLP_LDOEMMCCORE_PD_EN |
73 BIT_SLP_LDOEMMCIO_PD_EN |
74 BIT_SLP_LDODCXO_PD_EN |
75 BIT_SLP_LDOCON_PD_EN |
76 BIT_SLP_LDOVDD25_PD_EN |
77 //BIT_SLP_LDOVDD28_PD_EN |
78 //BIT_SLP_LODVDD18_PD_EN |
82 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
84 BIT_SLP_LDOLPREF_PD_EN |
85 BIT_SLP_LDOCLSG_PD_EN |
86 BIT_SLP_LDOUSB_PD_EN |
87 BIT_SLP_LDOCAMMOT_PD_EN |
88 BIT_SLP_LDOCAMIO_PD_EN |
89 BIT_SLP_LDOCAMD_PD_EN |
90 BIT_SLP_LDOCAMA_PD_EN |
91 BIT_SLP_LDOSIM2_PD_EN |
92 //BIT_SLP_LDOSIM1_PD_EN |
93 //BIT_SLP_LDOSIM0_PD_EN |
97 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
98 BIT_SLP_DCDCCORE_LP_EN |
99 BIT_SLP_DCDCMEM_LP_EN |
100 //BIT_SLP_DCDCARM_LP_EN |
101 //BIT_SLP_DCDCGEN_LP_EN |
102 //BIT_SLP_DCDCWPA_LP_EN |
103 //BIT_SLP_LDORF0_LP_EN |
104 //BIT_SLP_LDOEMMCCORE_LP_EN |
105 //BIT_SLP_LDOEMMCIO_LP_EN |
106 //BIT_SLP_LDODCXO_LP_EN |
107 //BIT_SLP_LDOCON_LP_EN |
108 //BIT_SLP_LDOVDD25_LP_EN |
109 //BIT_SLP_LDOVDD28_LP_EN |
110 //BIT_SLP_LDOVDD18_LP_EN |
113 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
115 //BIT_SLP_LDOCLSG_LP_EN |
116 //BIT_SLP_LDOUSB_LP_EN |
117 //BIT_SLP_LDOCAMMOT_LP_EN |
118 //BIT_SLP_LDOCAMIO_LP_EN |
119 //BIT_SLP_LDOCAMD_LP_EN |
120 //BIT_SLP_LDOCAMA_LP_EN |
121 //BIT_SLP_LDOSIM2_LP_EN |
122 //BIT_SLP_LDOSIM1_LP_EN |
123 //BIT_SLP_LDOSIM0_LP_EN |
124 //BIT_SLP_LDOSD_LP_EN |
126 /****************************************
127 * Following is CP LDO Sleep Control *
128 ****************************************/
129 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
131 BIT_LDO_DCXO_EXT_XTL1_EN |
132 BIT_LDO_DCXO_EXT_XTL0_EN |
133 BIT_LDO_DCXO_XTL2_EN |
134 BIT_LDO_DCXO_XTL0_EN |
135 //BIT_LDO_VDD18_EXT_XTL1_EN |
136 //BIT_LDO_VDD18_EXT_XTL0_EN |
137 //BIT_LDO_VDD18_XTL2_EN |
138 //BIT_LDO_VDD18_XTL0_EN |
139 //BIT_LDO_VDD28_EXT_XTL1_EN |
140 //BIT_LDO_VDD28_EXT_XTL0_EN |
141 //BIT_LDO_VDD28_XTL2_EN |
142 //BIT_LDO_VDD28_XTL0_EN |
145 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
146 BIT_LDO_RF0_EXT_XTL1_EN |
147 BIT_LDO_RF0_EXT_XTL0_EN |
148 BIT_LDO_RF0_XTL2_EN |
149 BIT_LDO_RF0_XTL0_EN |
150 //BIT_LDO_VDD25_EXT_XTL1_EN |
151 //BIT_LDO_VDD25_EXT_XTL0_EN |
152 BIT_LDO_VDD25_XTL2_EN |
153 BIT_LDO_VDD25_XTL0_EN |
154 //BIT_LDO_CON_EXT_XTL1_EN |
155 //BIT_LDO_CON_EXT_XTL0_EN |
156 //BIT_LDO_CON_XTL2_EN |
157 //BIT_LDO_CON_XTL0_EN |
160 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
161 //BIT_LDO_SIM2_EXT_XTL1_EN |
162 //BIT_LDO_SIM2_EXT_XTL0_EN |
163 //BIT_LDO_SIM2_XTL2_EN |
164 //BIT_LDO_SIM2_XTL0_EN |
165 //BIT_LDO_SIM1_EXT_XTL1_EN |
166 //BIT_LDO_SIM1_EXT_XTL0_EN |
167 //BIT_LDO_SIM1_XTL2_EN |
168 //BIT_LDO_SIM1_XTL0_EN |
169 //BIT_LDO_SIM0_EXT_XTL1_EN |
170 //BIT_LDO_SIM0_EXT_XTL0_EN |
171 //BIT_LDO_SIM0_XTL2_EN |
172 //BIT_LDO_SIM0_XTL0_EN |
175 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
176 //BIT_XO_EXT_XTL1_EN |
177 //BIT_XO_EXT_XTL0_EN |
180 //BIT_BG_EXT_XTL1_EN |
181 //BIT_BG_EXT_XTL0_EN |
186 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
187 //BIT_DCDC_WPA_EXT_XTL1_EN |
188 //BIT_DCDC_WPA_EXT_XTL0_EN |
189 //BIT_DCDC_WPA_XTL2_EN |
190 //BIT_DCDC_WPA_XTL0_EN |
191 //BIT_DCDC_MEM_EXT_XTL1_EN |
192 //BIT_DCDC_MEM_EXT_XTL0_EN |
193 //BIT_DCDC_MEM_XTL2_EN |
194 //BIT_DCDC_MEM_XTL0_EN |
195 //BIT_DCDC_GEN_EXT_XTL1_EN |
196 //BIT_DCDC_GEN_EXT_XTL0_EN |
197 //BIT_DCDC_GEN_XTL2_EN |
198 //BIT_DCDC_GEN_XTL0_EN |
199 //BIT_DCDC_CORE_EXT_XTL1_EN |
200 //BIT_DCDC_CORE_EXT_XTL0_EN |
201 BIT_DCDC_CORE_XTL2_EN |
202 BIT_DCDC_CORE_XTL0_EN |
204 /************************************************
205 * Following is AP/CP LDO D DIE Sleep Control *
206 *************************************************/
207 CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
215 CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
223 CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
231 CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
232 BIT_XTLBUF0_CP2_SEL |
233 BIT_XTLBUF0_CP1_SEL |
234 BIT_XTLBUF0_CP0_SEL |
239 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
240 BIT_XTLBUF1_CP2_SEL |
241 //BIT_XTLBUF1_CP1_SEL |
242 BIT_XTLBUF1_CP0_SEL |
247 CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
256 CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
265 CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
266 //BIT_TDPLL_REF_SEL |
268 //BIT_TDPLL_CP1_SEL |
274 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
283 CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
292 CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
293 //BIT_WIFIPLL1_REF_SEL |
294 BIT_WIFIPLL1_CP2_SEL |
295 //BIT_WIFIPLL1_CP1_SEL |
296 //BIT_WIFIPLL1_CP0_SEL |
297 //BIT_WIFIPLL1_AP_SEL |
301 CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
302 //BIT_WIFIPLL2_REF_SEL |
303 BIT_WIFIPLL2_CP2_SEL |
304 //BIT_WIFIPLL2_CP1_SEL |
305 //BIT_WIFIPLL2_CP0_SEL |
306 //BIT_WIFIPLL2_AP_SEL |
310 CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN,
320 BIT_CGM_153M6_AP_EN |
326 //BIT_CGM_WPLL_AP_EN |
327 //BIT_CGM_WIFIPLL1_AP_EN |
328 BIT_CGM_TDPLL_AP_EN |
329 //BIT_CGM_CPLL_AP_EN |
334 CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
335 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
336 BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
337 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
338 BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
342 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
343 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
344 BITS_PD_CA7_C0_PWR_ON_DLY(8) |
345 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
346 BITS_PD_CA7_C0_ISO_ON_DLY(2) |
350 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
351 BIT_PD_CA7_C1_FORCE_SHUTDOWN |
352 BITS_PD_CA7_C1_PWR_ON_DLY(8) |
353 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
354 BITS_PD_CA7_C1_ISO_ON_DLY(2) |
358 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
359 BIT_PD_CA7_C2_FORCE_SHUTDOWN |
360 BITS_PD_CA7_C2_PWR_ON_DLY(8) |
361 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
362 BITS_PD_CA7_C2_ISO_ON_DLY(2) |
366 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
367 BIT_PD_CA7_C3_FORCE_SHUTDOWN |
368 BITS_PD_CA7_C3_PWR_ON_DLY(8) |
369 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
370 BITS_PD_CA7_C3_ISO_ON_DLY(2) |
374 CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
375 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
376 BITS_PD_AP_SYS_PWR_ON_DLY(8) |
377 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
378 BITS_PD_AP_SYS_ISO_ON_DLY(6) |
382 CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
383 BIT_PD_MM_TOP_FORCE_SHUTDOWN |
384 BITS_PD_MM_TOP_PWR_ON_DLY(8) |
385 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
386 BITS_PD_MM_TOP_ISO_ON_DLY(4) |
390 CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
391 BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
392 BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
393 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
394 BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
398 CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
399 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
400 BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
401 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
402 BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
406 CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
407 BITS_XTL1_WAIT_CNT(0x39) |
408 BITS_XTL0_WAIT_CNT(0x39) |
412 CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
413 BITS_XTLBUF1_WAIT_CNT(7) |
414 BITS_XTLBUF0_WAIT_CNT(7) |
418 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
419 BITS_WPLL_WAIT_CNT(7) |
420 BITS_TDPLL_WAIT_CNT(7) |
421 BITS_DPLL_WAIT_CNT(7) |
422 BITS_MPLL_WAIT_CNT(7) |
426 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
427 BITS_WIFIPLL2_WAIT_CNT(7) |
428 BITS_WIFIPLL1_WAIT_CNT(7) |
429 BITS_CPLL_WAIT_CNT(7) |
433 ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
434 BITS_SLP_IN_WAIT_DCDCARM(9) |
435 BITS_SLP_OUT_WAIT_DCDCARM(8) |
439 /*work round sin0 disconnect*/
440 reg_val = CHIP_REG_GET(REG_AON_APB_SINDRV_CTRL);
441 reg_val |= BIT_SINDRV_ENA_SQUARE;
442 CHIP_REG_SET(REG_AON_APB_SINDRV_CTRL, reg_val);