1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
6 /***************************************************************************************************************************/
7 /* VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
8 /* AP x x v v v v v v v v v x v v v v v v v */
9 /* CP0 x x v v v x x x x v x x x x x x x x x */
10 /* CP1 x x v x x x x x x x x x x x x x x x x */
11 /* CP2 x x v v x v x x x v x x x x x x x x x */
12 /* EX0 x x x v x x x x x x x x x x x x x x x */
13 /* EX1 x x x x v x x x x x x x x x x x x x x */
14 /* EX2 x x x v x x x x x x x x x x x x x x x */
15 /***************************************************************************************************************************/
17 /***************************************************************************************************************************/
18 /* CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA LPGEN LPARM LPMEM LPCORE LPBG BG */
19 /* AP v v v v v v v v v v v x v v v v v v */
20 /* CP0 x x x x x x x x x x x x x x x x x x */
21 /* CP1 x x x x x x x x x x x x x x x x x x */
22 /* CP2 x x x x x x v v x x x x x x x x x x */
23 /* EX0 x x x x x x x x v x x x x x x x x x */
24 /* EX1 x x x x x x x x x x x x x x x x x x */
25 /* EX2 x x x x x x x x x x x x x x x x x x */
26 /***************************************************************************************************************************/
28 void init_ldo_sleep_gr(void)
32 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0x6e7f));
35 reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT);
38 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
46 //BIT_LDO_EMMCCORE_PD|
57 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0));
59 /**********************************************
60 * Following is AP LDO A DIE Sleep Control *
61 *********************************************/
62 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
64 //BIT_SLP_DCDCGEN_PD_EN |
65 BIT_SLP_DCDCWPA_PD_EN |
66 BIT_SLP_DCDCARM_PD_EN |
67 BIT_SLP_LDORF0_PD_EN |
68 BIT_SLP_LDOEMMCCORE_PD_EN |
69 BIT_SLP_LDOEMMCIO_PD_EN |
70 //BIT_SLP_LDODCXO_PD_EN |
71 BIT_SLP_LDOCON_PD_EN |
72 BIT_SLP_LDOVDD25_PD_EN |
73 //BIT_SLP_LDOVDD28_PD_EN |
74 //BIT_SLP_LODVDD18_PD_EN |
78 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
80 BIT_SLP_LDOLPREF_PD_EN |
81 BIT_SLP_LDOCLSG_PD_EN |
82 BIT_SLP_LDOUSB_PD_EN |
83 BIT_SLP_LDOCAMMOT_PD_EN |
84 BIT_SLP_LDOCAMIO_PD_EN |
85 BIT_SLP_LDOCAMD_PD_EN |
86 BIT_SLP_LDOCAMA_PD_EN |
87 BIT_SLP_LDOSIM2_PD_EN |
88 //BIT_SLP_LDOSIM1_PD_EN |
89 //BIT_SLP_LDOSIM0_PD_EN |
93 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
94 BIT_SLP_DCDCCORE_LP_EN |
95 BIT_SLP_DCDCMEM_LP_EN |
96 //BIT_SLP_DCDCARM_LP_EN |
97 //BIT_SLP_DCDCGEN_LP_EN |
98 //BIT_SLP_DCDCWPA_LP_EN |
99 //BIT_SLP_LDORF0_LP_EN |
100 //BIT_SLP_LDOEMMCCORE_LP_EN |
101 //BIT_SLP_LDOEMMCIO_LP_EN |
102 //BIT_SLP_LDODCXO_LP_EN |
103 //BIT_SLP_LDOCON_LP_EN |
104 //BIT_SLP_LDOVDD25_LP_EN |
105 //BIT_SLP_LDOVDD28_LP_EN |
106 //BIT_SLP_LDOVDD18_LP_EN |
109 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
111 //BIT_SLP_LDOCLSG_LP_EN |
112 //BIT_SLP_LDOUSB_LP_EN |
113 //BIT_SLP_LDOCAMMOT_LP_EN |
114 //BIT_SLP_LDOCAMIO_LP_EN |
115 //BIT_SLP_LDOCAMD_LP_EN |
116 //BIT_SLP_LDOCAMA_LP_EN |
117 //BIT_SLP_LDOSIM2_LP_EN |
118 //BIT_SLP_LDOSIM1_LP_EN |
119 //BIT_SLP_LDOSIM0_LP_EN |
120 //BIT_SLP_LDOSD_LP_EN |
122 /****************************************
123 * Following is CP LDO Sleep Control *
124 ****************************************/
125 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
127 //BIT_LDO_DCXO_EXT_XTL1_EN |
128 //BIT_LDO_DCXO_EXT_XTL0_EN |
129 //BIT_LDO_DCXO_XTL2_EN |
130 //BIT_LDO_DCXO_XTL0_EN |
131 //BIT_LDO_VDD18_EXT_XTL1_EN |
132 //BIT_LDO_VDD18_EXT_XTL0_EN |
133 //BIT_LDO_VDD18_XTL2_EN |
134 //BIT_LDO_VDD18_XTL0_EN |
135 //BIT_LDO_VDD28_EXT_XTL1_EN |
136 //BIT_LDO_VDD28_EXT_XTL0_EN |
137 //BIT_LDO_VDD28_XTL2_EN |
138 //BIT_LDO_VDD28_XTL0_EN |
141 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
142 BIT_LDO_RF0_EXT_XTL1_EN |
143 BIT_LDO_RF0_EXT_XTL0_EN |
144 BIT_LDO_RF0_XTL2_EN |
145 BIT_LDO_RF0_XTL0_EN |
146 //BIT_LDO_VDD25_EXT_XTL1_EN |
147 //BIT_LDO_VDD25_EXT_XTL0_EN |
148 BIT_LDO_VDD25_XTL2_EN |
149 BIT_LDO_VDD25_XTL0_EN |
150 //BIT_LDO_CON_EXT_XTL1_EN |
151 //BIT_LDO_CON_EXT_XTL0_EN |
152 BIT_LDO_CON_XTL2_EN |
153 BIT_LDO_CON_XTL0_EN |
156 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
157 //BIT_LDO_SIM2_EXT_XTL1_EN |
158 //BIT_LDO_SIM2_EXT_XTL0_EN |
159 //BIT_LDO_SIM2_XTL2_EN |
160 //BIT_LDO_SIM2_XTL0_EN |
161 //BIT_LDO_SIM1_EXT_XTL1_EN |
162 //BIT_LDO_SIM1_EXT_XTL0_EN |
163 //BIT_LDO_SIM1_XTL2_EN |
164 //BIT_LDO_SIM1_XTL0_EN |
165 //BIT_LDO_SIM0_EXT_XTL1_EN |
166 //BIT_LDO_SIM0_EXT_XTL0_EN |
167 //BIT_LDO_SIM0_XTL2_EN |
168 //BIT_LDO_SIM0_XTL0_EN |
171 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
172 //BIT_XO_EXT_XTL1_EN |
173 //BIT_XO_EXT_XTL0_EN |
176 //BIT_BG_EXT_XTL1_EN |
177 //BIT_BG_EXT_XTL0_EN |
182 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
183 //BIT_DCDC_WPA_EXT_XTL1_EN |
184 //BIT_DCDC_WPA_EXT_XTL0_EN |
185 //BIT_DCDC_WPA_XTL2_EN |
186 //BIT_DCDC_WPA_XTL0_EN |
187 //BIT_DCDC_MEM_EXT_XTL1_EN |
188 //BIT_DCDC_MEM_EXT_XTL0_EN |
189 //BIT_DCDC_MEM_XTL2_EN |
190 //BIT_DCDC_MEM_XTL0_EN |
191 //BIT_DCDC_GEN_EXT_XTL1_EN |
192 //BIT_DCDC_GEN_EXT_XTL0_EN |
193 //BIT_DCDC_GEN_XTL2_EN |
194 //BIT_DCDC_GEN_XTL0_EN |
195 //BIT_DCDC_CORE_EXT_XTL1_EN |
196 //BIT_DCDC_CORE_EXT_XTL0_EN |
197 BIT_DCDC_CORE_XTL2_EN |
198 BIT_DCDC_CORE_XTL0_EN |
200 /************************************************
201 * Following is AP/CP LDO D DIE Sleep Control *
202 *************************************************/
203 CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
211 CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
219 CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
227 CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
228 BIT_XTLBUF0_CP2_SEL |
229 //BIT_XTLBUF0_CP1_SEL |
230 BIT_XTLBUF0_CP0_SEL |
235 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
236 //BIT_XTLBUF1_CP2_SEL |
237 //BIT_XTLBUF1_CP1_SEL |
238 //BIT_XTLBUF1_CP0_SEL |
243 CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
252 CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
261 CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
262 //BIT_TDPLL_REF_SEL |
264 //BIT_TDPLL_CP1_SEL |
270 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
279 CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
288 CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
289 //BIT_WIFIPLL1_REF_SEL |
290 BIT_WIFIPLL1_CP2_SEL |
291 //BIT_WIFIPLL1_CP1_SEL |
292 //BIT_WIFIPLL1_CP0_SEL |
293 //BIT_WIFIPLL1_AP_SEL |
297 CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
298 //BIT_WIFIPLL2_REF_SEL |
299 BIT_WIFIPLL2_CP2_SEL |
300 //BIT_WIFIPLL2_CP1_SEL |
301 //BIT_WIFIPLL2_CP0_SEL |
302 //BIT_WIFIPLL2_AP_SEL |
306 CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN,
316 BIT_CGM_153M6_AP_EN |
322 //BIT_CGM_WPLL_AP_EN |
323 //BIT_CGM_WIFIPLL1_AP_EN |
324 BIT_CGM_TDPLL_AP_EN |
325 //BIT_CGM_CPLL_AP_EN |
330 CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
331 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
332 BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
333 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
334 BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
338 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
339 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
340 BITS_PD_CA7_C0_PWR_ON_DLY(8) |
341 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
342 BITS_PD_CA7_C0_ISO_ON_DLY(2) |
346 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
347 BIT_PD_CA7_C1_FORCE_SHUTDOWN |
348 BITS_PD_CA7_C1_PWR_ON_DLY(8) |
349 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
350 BITS_PD_CA7_C1_ISO_ON_DLY(2) |
354 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
355 BIT_PD_CA7_C2_FORCE_SHUTDOWN |
356 BITS_PD_CA7_C2_PWR_ON_DLY(8) |
357 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
358 BITS_PD_CA7_C2_ISO_ON_DLY(2) |
362 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
363 BIT_PD_CA7_C3_FORCE_SHUTDOWN |
364 BITS_PD_CA7_C3_PWR_ON_DLY(8) |
365 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
366 BITS_PD_CA7_C3_ISO_ON_DLY(2) |
370 CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
371 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
372 BITS_PD_AP_SYS_PWR_ON_DLY(8) |
373 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
374 BITS_PD_AP_SYS_ISO_ON_DLY(6) |
378 CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
379 BIT_PD_MM_TOP_FORCE_SHUTDOWN |
380 BITS_PD_MM_TOP_PWR_ON_DLY(8) |
381 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
382 BITS_PD_MM_TOP_ISO_ON_DLY(4) |
386 CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
387 BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
388 BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
389 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
390 BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
394 CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
395 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
396 BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
397 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
398 BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
402 CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
403 BITS_XTL1_WAIT_CNT(0x39) |
404 BITS_XTL0_WAIT_CNT(0x39) |
408 CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
409 BITS_XTLBUF1_WAIT_CNT(7) |
410 BITS_XTLBUF0_WAIT_CNT(7) |
414 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
415 BITS_WPLL_WAIT_CNT(7) |
416 BITS_TDPLL_WAIT_CNT(7) |
417 BITS_DPLL_WAIT_CNT(7) |
418 BITS_MPLL_WAIT_CNT(7) |
422 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
423 BITS_WIFIPLL2_WAIT_CNT(7) |
424 BITS_WIFIPLL1_WAIT_CNT(7) |
425 BITS_CPLL_WAIT_CNT(7) |
429 ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
430 BITS_SLP_IN_WAIT_DCDCARM(9) |
431 BITS_SLP_OUT_WAIT_DCDCARM(8) |