2 * This file is produced by tools!!
4 * Copyright (C) 2012 Spreadtrum Communications Inc.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <asm/arch/pinmap.h>
22 struct other_pin_ctr_reg {
23 uint32_t reg; /*pin register offset*/
26 uint32_t wpus:1; /*[12] pull up resistor select*/
29 uint32_t func_sel:2; /*[5:4]function slect.*/
30 /*value of .func_sel*/
31 #define FUNC0 0 /*function0*/
32 #define FUNC1 1 /*function1*/
33 #define FUNC2 2 /*function2*/
34 #define FUNC3 3 /*function3*/
36 uint32_t func_wpu_wpd:2; /*[7:6] weakly pull up/down for function mode*/
37 /*value of .func_wpu_wpd*/
38 #define FUNC_WPU (1<<1) /*weakly pull up for function mode*/
39 #define FUNC_WPD (1<<0) /*weakly pull down for function mode*/
41 uint32_t slp_wpu_wpd:2; /*[3:2]weak pull up/down for chip deep sleep mode*/
42 /*value of .slp_wpu_wpd*/
43 #define SLP_WPU (1<<1) /*weakly pull up for chip deep sleep mode*/
44 #define SLP_WPD (1<<0) /*weakly pull down for chip deep sleep mode*/
46 uint32_t drv:3; /*[10:8] driver strength select.*/
57 uint32_t ie_oe:2; /*[1:0]input/output enable for chip deep sleep mode*/
59 #define SLP_IE (1<<1) /* input enable for chip deep sleep mode*/
60 #define SLP_OE (1<<0) /*output enable for chip deep sleep mode*/
62 uint32_t se:1; /*[11] schmitt trigger input enalbe*/
65 uint32_t slp_en:4; /*[16:13] sleep mode bit map: SLP_AP|SLP_CP0|SLP_CP1|SLP_CP2 */
66 #define SLP_AP BIT_0 /* sleep with AP*/
67 #define SLP_CP0 BIT_1 /* sleep with CP0*/
68 #define SLP_CP1 BIT_2 /* sleep with CP1*/
69 #define SLP_CP2 BIT_3 /* sleep with CP2*/
73 struct other_pin_ctr_reg other[] = {
75 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
76 {REG_PIN_TRACECLK, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
77 {REG_PIN_TRACECTRL, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
78 {REG_PIN_TRACEDAT0, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
79 {REG_PIN_TRACEDAT1, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
80 {REG_PIN_TRACEDAT2, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
81 {REG_PIN_TRACEDAT3, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
82 {REG_PIN_TRACEDAT4, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
83 {REG_PIN_TRACEDAT5, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
84 {REG_PIN_TRACEDAT6, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
86 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
87 {REG_PIN_TRACEDAT7, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
88 {REG_PIN_U0TXD, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
89 {REG_PIN_U0RXD, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
90 {REG_PIN_U0CTS, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
91 {REG_PIN_U0RTS, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
92 {REG_PIN_U1TXD, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
93 {REG_PIN_U1RXD, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
94 {REG_PIN_U2TXD, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
95 {REG_PIN_U2RXD, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
96 {REG_PIN_U3TXD, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
98 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
99 {REG_PIN_U3RXD, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
100 {REG_PIN_U3CTS, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
101 {REG_PIN_U3RTS, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
102 {REG_PIN_EXTINT2, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
103 {REG_PIN_EXTINT3, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
104 {REG_PIN_RFSDA2, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
105 {REG_PIN_RFSCK2, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
106 {REG_PIN_RFSEN2, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
107 {REG_PIN_CP2_RFCTL0, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
108 {REG_PIN_CP2_RFCTL1, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
110 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
111 {REG_PIN_CP2_RFCTL2, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
112 {REG_PIN_FM_RXIQD0, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
113 {REG_PIN_FM_RXIQD1, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
114 {REG_PIN_WIFI_AGCGAIN0, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
115 {REG_PIN_WIFI_AGCGAIN1, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
116 {REG_PIN_WIFI_AGCGAIN2, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
117 {REG_PIN_WIFI_AGCGAIN3, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
118 {REG_PIN_WIFI_AGCGAIN4, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
119 {REG_PIN_WIFI_AGCGAIN5, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
120 {REG_PIN_WIFI_AGCGAIN6, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
122 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
123 {REG_PIN_WBENA, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
124 {REG_PIN_WBENB, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
125 {REG_PIN_GPSREAL, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
126 {REG_PIN_GPSIMAG, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
127 {REG_PIN_GPSCLK, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
128 {REG_PIN_RFSDA0, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
129 {REG_PIN_RFSCK0, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
130 {REG_PIN_RFSEN0, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
131 {REG_PIN_RFSDA1, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
132 {REG_PIN_RFSCK1, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
134 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
135 {REG_PIN_RFSEN1, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
136 {REG_PIN_CP1_RFCTL0, PIN_NULL, FUNC0, PIN_NULL, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
137 {REG_PIN_CP1_RFCTL1, PIN_NULL, FUNC0, PIN_NULL, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
138 {REG_PIN_CP1_RFCTL2, PIN_NULL, FUNC0, PIN_NULL, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
139 {REG_PIN_CP1_RFCTL3, PIN_NULL, FUNC0, PIN_NULL, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
140 {REG_PIN_CP1_RFCTL4, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
141 {REG_PIN_CP1_RFCTL5, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
142 {REG_PIN_CP1_RFCTL6, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
143 {REG_PIN_CP1_RFCTL7, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
144 {REG_PIN_CP1_RFCTL8, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
146 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
147 {REG_PIN_CP1_RFCTL9, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
148 {REG_PIN_CP1_RFCTL10, PIN_NULL, FUNC1, PIN_NULL, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
149 {REG_PIN_CP1_RFCTL11, PIN_NULL, FUNC1, PIN_NULL, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
150 {REG_PIN_CP1_RFCTL12, PIN_NULL, FUNC1, PIN_NULL, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
151 {REG_PIN_CP1_RFCTL13, PIN_NULL, FUNC1, PIN_NULL, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
152 {REG_PIN_CP1_RFCTL14, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
153 {REG_PIN_CP1_RFCTL15, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
154 {REG_PIN_CP0_RFCTL0, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
155 {REG_PIN_CP0_RFCTL1, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
156 {REG_PIN_CP0_RFCTL2, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
158 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
159 {REG_PIN_CP0_RFCTL3, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
160 {REG_PIN_CP0_RFCTL4, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
161 {REG_PIN_CP0_RFCTL5, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
162 {REG_PIN_CP0_RFCTL6, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
163 {REG_PIN_CP0_RFCTL7, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
164 {REG_PIN_XTLEN, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
165 {REG_PIN_GPIO6, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
166 {REG_PIN_GPIO7, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
167 {REG_PIN_GPIO8, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
168 {REG_PIN_GPIO9, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
170 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
171 {REG_PIN_U4TXD, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
172 {REG_PIN_U4RXD, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
173 {REG_PIN_U4CTS, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
174 {REG_PIN_U4RTS, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
175 {REG_PIN_SCL3, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
176 {REG_PIN_SDA3, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
177 {REG_PIN_SPI0_CSN, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
178 {REG_PIN_SPI0_DO, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
179 {REG_PIN_SPI0_DI, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
180 {REG_PIN_SPI0_CLK, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
182 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
183 {REG_PIN_EXTINT0, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
184 {REG_PIN_EXTINT1, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
185 {REG_PIN_SCL1, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
186 {REG_PIN_SDA1, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
187 {REG_PIN_GPIO0, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
188 {REG_PIN_GPIO1, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
189 {REG_PIN_GPIO2, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
190 {REG_PIN_GPIO3, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
191 {REG_PIN_SIMCLK0, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
192 {REG_PIN_SIMDA0, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
194 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
195 {REG_PIN_SIMRST0, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
196 {REG_PIN_SIMCLK1, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
197 {REG_PIN_SIMDA1, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
198 {REG_PIN_SIMRST1, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
199 {REG_PIN_SIMCLK2, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
200 {REG_PIN_SIMDA2, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
201 {REG_PIN_SIMRST2, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
202 {REG_PIN_MEMS_MIC_CLK0, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L2, PIN_NULL, PIN_NULL, PIN_NULL},
203 {REG_PIN_MEMS_MIC_DATA0, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L2, PIN_NULL, PIN_NULL, PIN_NULL},
204 {REG_PIN_MEMS_MIC_CLK1, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L2, PIN_NULL, PIN_NULL, PIN_NULL},
206 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
207 {REG_PIN_MEMS_MIC_DATA1, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L2, PIN_NULL, PIN_NULL, PIN_NULL},
208 {REG_PIN_SD1_CLK, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L2, SLP_OE, PIN_NULL, PIN_NULL},
209 {REG_PIN_SD1_CMD, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
210 {REG_PIN_SD1_D0, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
211 {REG_PIN_SD1_D1, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
212 {REG_PIN_SD1_D2, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
213 {REG_PIN_SD1_D3, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
214 {REG_PIN_SD0_D3, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
215 {REG_PIN_SD0_D2, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
216 {REG_PIN_SD0_CMD, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
218 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
219 {REG_PIN_SD0_D0, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
220 {REG_PIN_SD0_D1, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
221 {REG_PIN_SD0_CLK1, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
222 {REG_PIN_SD0_CLK0, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L2, SLP_OE, PIN_NULL, PIN_NULL},
223 {REG_PIN_PTEST, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
224 {REG_PIN_ANA_INT, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
225 {REG_PIN_EXT_RST_B, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
226 {REG_PIN_CHIP_SLEEP, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
227 {REG_PIN_XTL_BUF_EN0, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
228 {REG_PIN_XTL_BUF_EN1, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
230 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
231 {REG_PIN_XTL_BUF_EN2, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
232 {REG_PIN_CLK_32K, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
233 {REG_PIN_AUD_SCLK, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
234 {REG_PIN_AUD_DANGL, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
235 {REG_PIN_AUD_DANGR, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
236 {REG_PIN_AUD_ADD0, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
237 {REG_PIN_AUD_ADSYNC, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
238 {REG_PIN_AUD_DAD1, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
239 {REG_PIN_AUD_DAD0, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
240 {REG_PIN_AUD_DASYNC, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
242 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
243 {REG_PIN_ADI_D, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
244 {REG_PIN_ADI_SYNC, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
245 {REG_PIN_ADI_SCLK, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
246 {REG_PIN_LCD_CSN1, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
247 {REG_PIN_LCD_CSN0, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
248 {REG_PIN_LCD_RSTN, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
249 {REG_PIN_LCD_CD, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
250 {REG_PIN_LCD_FMARK, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
251 {REG_PIN_LCD_WRN, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
252 {REG_PIN_LCD_RDN, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
254 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
255 {REG_PIN_LCD_D0, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
256 {REG_PIN_LCD_D1, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
257 {REG_PIN_LCD_D2, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
258 {REG_PIN_LCD_D3, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
259 {REG_PIN_LCD_D4, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
260 {REG_PIN_LCD_D5, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
261 {REG_PIN_LCD_D6, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
262 {REG_PIN_LCD_D7, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
263 {REG_PIN_LCD_D8, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
264 {REG_PIN_LCD_D9, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
266 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
267 {REG_PIN_LCD_D10, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
268 {REG_PIN_LCD_D11, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
269 {REG_PIN_LCD_D12, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
270 {REG_PIN_LCD_D13, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
271 {REG_PIN_LCD_D14, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
272 {REG_PIN_LCD_D15, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
273 {REG_PIN_LCD_D16, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
274 {REG_PIN_LCD_D17, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
275 {REG_PIN_LCD_D18, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
276 {REG_PIN_LCD_D19, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
278 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
279 {REG_PIN_LCD_D20, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
280 {REG_PIN_LCD_D21, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
281 {REG_PIN_LCD_D22, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
282 {REG_PIN_LCD_D23, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
283 {REG_PIN_SPI2_CSN, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
284 {REG_PIN_SPI2_DO, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
285 {REG_PIN_SPI2_DI, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
286 {REG_PIN_SPI2_CLK, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
287 {REG_PIN_EMMC_CLK, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L2, SLP_OE, PIN_NULL, PIN_NULL},
288 {REG_PIN_EMMC_CMD, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
290 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
291 {REG_PIN_EMMC_D0, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
292 {REG_PIN_EMMC_D1, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
293 {REG_PIN_EMMC_D2, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
294 {REG_PIN_EMMC_D3, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
295 {REG_PIN_EMMC_D4, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
296 {REG_PIN_EMMC_D5, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
297 {REG_PIN_EMMC_D6, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
298 {REG_PIN_EMMC_D7, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
299 {REG_PIN_EMMC_RST, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L2, PIN_NULL, PIN_NULL, PIN_NULL},
300 {REG_PIN_NFWPN, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
302 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
303 {REG_PIN_NFRB, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
304 {REG_PIN_NFCLE, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
305 {REG_PIN_NFALE, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
306 {REG_PIN_NFCEN0, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
307 {REG_PIN_NFCEN1, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
308 {REG_PIN_NFREN, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
309 {REG_PIN_NFWEN, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
310 {REG_PIN_NFD0, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L2, PIN_NULL, PIN_NULL, PIN_NULL},
311 {REG_PIN_NFD1, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L2, PIN_NULL, PIN_NULL, PIN_NULL},
312 {REG_PIN_NFD2, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L2, PIN_NULL, PIN_NULL, PIN_NULL},
314 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
315 {REG_PIN_NFD3, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L2, PIN_NULL, PIN_NULL, PIN_NULL},
316 {REG_PIN_NFD4, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
317 {REG_PIN_NFD5, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
318 {REG_PIN_NFD6, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
319 {REG_PIN_NFD7, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
320 {REG_PIN_NFD8, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
321 {REG_PIN_NFD9, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
322 {REG_PIN_NFD10, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
323 {REG_PIN_NFD11, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
324 {REG_PIN_NFD12, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
326 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
327 {REG_PIN_NFD13, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
328 {REG_PIN_NFD14, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
329 {REG_PIN_NFD15, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
330 {REG_PIN_CCIRCK0, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
331 {REG_PIN_CCIRCK1, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
332 {REG_PIN_CCIRMCLK, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
333 {REG_PIN_CCIRHS, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
334 {REG_PIN_CCIRVS, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
335 {REG_PIN_CCIRD0, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
336 {REG_PIN_CCIRD1, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
338 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
339 {REG_PIN_CCIRD2, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
340 {REG_PIN_CCIRD3, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
341 {REG_PIN_CCIRD4, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
342 {REG_PIN_CCIRD5, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
343 {REG_PIN_CCIRD6, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
344 {REG_PIN_CCIRD7, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
345 {REG_PIN_CCIRD8, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
346 {REG_PIN_CCIRD9, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
347 {REG_PIN_CCIRRST, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
348 {REG_PIN_CCIRPD1, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
350 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
351 {REG_PIN_CCIRPD0, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
352 {REG_PIN_SCL0, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
353 {REG_PIN_SDA0, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
354 {REG_PIN_KEYOUT0, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
355 {REG_PIN_KEYOUT1, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
356 {REG_PIN_KEYOUT2, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
357 {REG_PIN_KEYOUT3, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
358 {REG_PIN_KEYOUT4, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
359 {REG_PIN_KEYOUT5, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
360 {REG_PIN_KEYOUT6, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
362 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
363 {REG_PIN_KEYOUT7, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
364 {REG_PIN_KEYIN0, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
365 {REG_PIN_KEYIN1, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
366 {REG_PIN_KEYIN2, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
367 {REG_PIN_KEYIN3, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
368 {REG_PIN_KEYIN4, PIN_NULL, FUNC3, PIN_NULL, PIN_NULL, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
369 {REG_PIN_KEYIN5, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
370 {REG_PIN_KEYIN6, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
371 {REG_PIN_KEYIN7, PIN_NULL, FUNC3, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
372 {REG_PIN_GPIO4, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
374 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
375 {REG_PIN_GPIO5, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
376 {REG_PIN_SCL2, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
377 {REG_PIN_SDA2, PIN_WPUS, FUNC0, FUNC_WPU, SLP_WPU, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
378 {REG_PIN_CLK_AUX0, PIN_NULL, FUNC0, PIN_NULL, PIN_NULL, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
379 {REG_PIN_IIS0DI, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
380 {REG_PIN_IIS0DO, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
381 {REG_PIN_IIS0CLK, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
382 {REG_PIN_IIS0LRCK, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
383 {REG_PIN_IIS0MCK, PIN_NULL, FUNC2, PIN_NULL, PIN_NULL, DS_L1, SLP_OE, PIN_NULL, PIN_NULL},
384 {REG_PIN_IIS1DI, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
386 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
387 {REG_PIN_IIS1DO, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
388 {REG_PIN_IIS1CLK, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
389 {REG_PIN_IIS1LRCK, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
390 {REG_PIN_IIS1MCK, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
391 {REG_PIN_IIS2DI, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
392 {REG_PIN_IIS2DO, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
393 {REG_PIN_IIS2CLK, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
394 {REG_PIN_IIS2LRCK, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
395 {REG_PIN_IIS2MCK, PIN_NULL, FUNC0, FUNC_WPD, SLP_WPD, DS_L1, SLP_IE, PIN_NULL, PIN_NULL},
396 {REG_PIN_MTDO, PIN_NULL, FUNC0, PIN_NULL, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
398 /* reg |pin pull up|function|func pull up|sleep pull up|drv level|sleep i/o enable|schmitt enable|sleep enable */
399 {REG_PIN_MTDI, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
400 {REG_PIN_MTCK, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
401 {REG_PIN_MTMS, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
402 {REG_PIN_MTRST_N, PIN_NULL, FUNC0, FUNC_WPU, SLP_WPD, DS_L1, PIN_NULL, PIN_NULL, PIN_NULL},
406 extern void pinctrl_init(void);
417 for (i = 0; i < sizeof(other)/sizeof(other[0]); i++) {
418 v = ((other[i].slp_en & 0xF) << 13); /*[16:13]*/
419 v |= ((other[i].wpus & 1) << 12); /*[12]*/
420 v |= ((other[i].se & 1) << 11); /*[11]e*/
421 v |= ((other[i].drv & 7) << 8); /*[10:8]*/
422 v |= ((other[i].func_wpu_wpd & 3)<< 6); /*[7:6]*/
423 v |= ((other[i].func_sel & 3) << 4); /*[5:4]*/
424 v |= ((other[i].slp_wpu_wpd & 3) << 2); /*[3:2]*/
425 v |= ((other[i].ie_oe & 3) << 0); /*[1:0]*/
427 __raw_writel(v, CTL_PIN_BASE + other[i].reg);