1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
5 /***************************************************************************************************************************/
6 /* VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
7 /* AP x x v v v v v v v v v x v v v v v v v */
8 /* CP0 x x v v v x x x x v x x x x x x x x x */
9 /* CP1 x x v x x x x x x x x x x x x x x x x */
10 /* CP2 x x v v x v x x x v x x x x x x x x x */
11 /* EX0 x x x v x x x x x x x x x x x x x x x */
12 /* EX1 x x x x v x x x x x x x x x x x x x x */
13 /* EX2 x x x v x x x x x x x x x x x x x x x */
14 /***************************************************************************************************************************/
16 /***************************************************************************************************************************/
17 /* CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA LPGEN LPARM LPMEM LPCORE LPBG BG */
18 /* AP v v v v v v v v v v v x v v v v v v */
19 /* CP0 x x x x x x x x x x x x x x x x x x */
20 /* CP1 x x x x x x x x x x x x x x x x x x */
21 /* CP2 x x x x x x v v x x x x x x x x x x */
22 /* EX0 x x x x x x x x v x x x x x x x x x */
23 /* EX1 x x x x x x x x x x x x x x x x x x */
24 /* EX2 x x x x x x x x x x x x x x x x x x */
25 /***************************************************************************************************************************/
26 int set_default_regulator(void)
28 regulator_set_voltage("vddgen",2100);
31 void init_ldo_sleep_gr(void)
34 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
35 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
36 BITS_PWR_WR_PROT_VALUE(0x6e7f) |
40 while((ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT) != BIT_PWR_WR_PROT);
42 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
44 BIT_DCDC_TOPCLK6M_PD |
51 //BIT_LDO_EMMCCORE_PD |
62 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
63 BITS_PWR_WR_PROT_VALUE(0x0000) |
67 ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
84 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
86 BIT_SLP_DCDCRF_PD_EN |
87 BIT_SLP_DCDCCON_PD_EN |
88 //BIT_SLP_DCDCGEN_PD_EN |
89 //BIT_SLP_DCDCWPA_PD_EN |
90 BIT_SLP_DCDCARM_PD_EN |
91 BIT_SLP_LDOVDD25_PD_EN |
92 BIT_SLP_LDORF0_PD_EN |
93 BIT_SLP_LDOEMMCCORE_PD_EN |
94 //BIT_SLP_LDOGEN0_PD_EN |
95 BIT_SLP_LDODCXO_PD_EN |
96 BIT_SLP_LDOGEN1_PD_EN |
97 BIT_SLP_LDOWIFIPA_PD_EN |
98 //BIT_SLP_LDOVDD28_PD_EN |
99 //BIT_SLP_LDOVDD18_PD_EN |
102 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
104 BIT_SLP_LDOLPREF_PD_EN |
105 BIT_SLP_LDOSDCORE_PD_EN |
106 BIT_SLP_LDOUSB_PD_EN |
107 BIT_SLP_LDOCAMMOT_PD_EN |
108 BIT_SLP_LDOCAMIO_PD_EN |
109 BIT_SLP_LDOCAMD_PD_EN |
110 BIT_SLP_LDOCAMA_PD_EN |
111 //BIT_SLP_LDOSIM2_PD_EN |
112 //BIT_SLP_LDOSIM1_PD_EN |
113 //BIT_SLP_LDOSIM0_PD_EN |
114 BIT_SLP_LDOSDIO_PD_EN |
117 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
118 //BIT_SLP_DCDCRF_LP_EN |
119 //BIT_SLP_DCDCCON_LP_EN |
120 BIT_SLP_DCDCCORE_LP_EN |
121 BIT_SLP_DCDCMEM_LP_EN |
122 //BIT_SLP_DCDCARM_LP_EN |
123 BIT_SLP_DCDCGEN_LP_EN |
124 //BIT_SLP_DCDCWPA_LP_EN |
125 //BIT_SLP_LDORF0_LP_EN |
126 //BIT_SLP_LDOEMMCCORE_LP_EN |
127 //BIT_SLP_LDOGEN0_LP_EN |
128 //BIT_SLP_LDODCXO_LP_EN |
129 //BIT_SLP_LDOGEN1_LP_EN |
130 //BIT_SLP_LDOWIFIPA_LP_EN |
131 BIT_SLP_LDOVDD28_LP_EN |
132 //BIT_SLP_LDOVDD18_LP_EN |
135 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
137 //BIT_LDOVDD25_LP_EN_SW |
138 //BIT_LDOSDCORE_LP_EN_SW |
139 //BIT_LDOUSB_LP_EN_SW |
140 //BIT_SLP_LDOVDD25_LP_EN |
141 //BIT_SLP_LDOSDCORE_LP_EN |
142 //BIT_SLP_LDOUSB_LP_EN |
143 //BIT_SLP_LDOCAMMOT_LP_EN |
144 //BIT_SLP_LDOCAMIO_LP_EN |
145 //BIT_SLP_LDOCAMD_LP_EN |
146 //BIT_SLP_LDOCAMA_LP_EN |
147 //BIT_SLP_LDOSIM2_LP_EN |
148 //BIT_SLP_LDOSIM1_LP_EN |
149 //BIT_SLP_LDOSIM0_LP_EN |
150 //BIT_SLP_LDOSDIO_LP_EN |
153 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
154 //BIT_LDOCAMIO_LP_EN_SW |
155 //BIT_LDOCAMMOT_LP_EN_SW |
156 //BIT_LDOCAMD_LP_EN_SW |
157 //BIT_LDOCAMA_LP_EN_SW |
158 //BIT_LDOSIM2_LP_EN_SW |
159 //BIT_LDOSIM1_LP_EN_SW |
160 //BIT_LDOSIM0_LP_EN_SW |
161 //BIT_LDOSDIO_LP_EN_SW |
162 //BIT_LDORF0_LP_EN_SW |
163 //BIT_LDOEMMCCORE_LP_EN_SW |
164 //BIT_LDOGEN0_LP_EN_SW |
165 //BIT_LDODCXO_LP_EN_SW |
166 //BIT_LDOGEN1_LP_EN_SW |
167 //BIT_LDOWIFIPA_LP_EN_SW |
168 //BIT_LDOVDD28_LP_EN_SW |
169 //BIT_LDOVDD18_LP_EN_SW |
172 ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
173 BIT_SLP_XTLBUF_PD_EN |
175 BITS_XTL_WAIT(0x32) |
179 /****************************************
180 * Following is CP LDO Sleep Control *
181 ****************************************/
182 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
184 //BIT_LDO_GEN0_EXT_XTL0_EN |
185 //BIT_LDO_GEN0_XTL1_EN |
186 //BIT_LDO_GEN0_XTL0_EN |
187 //BIT_LDO_GEN1_EXT_XTL0_EN |
188 //BIT_LDO_GEN1_XTL1_EN |
189 BIT_LDO_GEN1_XTL0_EN |
190 BIT_LDO_DCXO_EXT_XTL0_EN |
191 BIT_LDO_DCXO_XTL1_EN |
192 BIT_LDO_DCXO_XTL0_EN |
193 //BIT_LDO_VDD18_EXT_XTL0_EN |
194 //BIT_LDO_VDD18_XTL1_EN |
195 //BIT_LDO_VDD18_XTL0_EN |
196 //BIT_LDO_VDD28_EXT_XTL0_EN |
197 //BIT_LDO_VDD28_XTL1_EN |
198 //BIT_LDO_VDD28_XTL0_EN |
201 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
202 BIT_LDO_RF0_EXT_XTL0_EN |
203 BIT_LDO_RF0_XTL1_EN |
204 BIT_LDO_RF0_XTL0_EN |
205 BIT_LDO_WIFIPA_EXT_XTL0_EN |
206 //BIT_LDO_WIFIPA_XTL1_EN |
207 //BIT_LDO_WIFIPA_XTL0_EN |
208 //BIT_LDO_SIM2_EXT_XTL0_EN |
209 //BIT_LDO_SIM2_XTL1_EN |
210 //BIT_LDO_SIM2_XTL0_EN |
211 //BIT_LDO_SIM1_EXT_XTL0_EN |
212 //BIT_LDO_SIM1_XTL1_EN |
213 //BIT_LDO_SIM1_XTL0_EN |
214 //BIT_LDO_SIM0_EXT_XTL0_EN |
215 //BIT_LDO_SIM0_XTL1_EN |
216 //BIT_LDO_SIM0_XTL0_EN |
219 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
220 BIT_LDO_VDD25_EXT_XTL0_EN |
221 BIT_LDO_VDD25_XTL1_EN |
222 BIT_LDO_VDD25_XTL0_EN |
223 BIT_DCDC_RF_EXT_XTL0_EN |
224 BIT_DCDC_RF_XTL1_EN |
225 BIT_DCDC_RF_XTL0_EN |
234 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
235 BIT_DCDC_CON_EXT_XTL0_EN |
236 BIT_DCDC_CON_XTL1_EN |
237 BIT_DCDC_CON_XTL0_EN |
238 //BIT_DCDC_WPA_EXT_XTL0_EN |
239 //BIT_DCDC_WPA_XTL1_EN |
240 //BIT_DCDC_WPA_XTL0_EN |
241 BIT_DCDC_MEM_EXT_XTL0_EN |
242 BIT_DCDC_MEM_XTL1_EN |
243 BIT_DCDC_MEM_XTL0_EN |
244 BIT_DCDC_GEN_EXT_XTL0_EN |
245 BIT_DCDC_GEN_XTL1_EN |
246 BIT_DCDC_GEN_XTL0_EN |
247 BIT_DCDC_CORE_EXT_XTL0_EN |
248 BIT_DCDC_CORE_XTL1_EN |
249 BIT_DCDC_CORE_XTL0_EN |
253 /*add by sam.sun, vddsim2 value 2.8v, bit15~bit8:a0*/
254 ANA_REG_SET(ANA_REG_GLB_LDO_V_CTRL5,
255 BITS_LDO_SIM2_V(0xa0) |
260 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR,
261 //BIT_LDO_AVDD18_PD_RTCCLR |
262 BIT_DCDC_OTP_PD_RTCCLR |
263 //BIT_DCDC_WRF_PD_RTCCLR |
264 BIT_DCDC_GEN_PD_RTCCLR |
265 BIT_DCDC_MEM_PD_RTCCLR |
266 BIT_DCDC_ARM_PD_RTCCLR |
267 BIT_DCDC_CORE_PD_RTCCLR|
268 BIT_LDO_EMMCCORE_PD_RTCCLR |
269 BIT_LDO_EMMCIO_PD_RTCCLR |
270 BIT_LDO_RF2_PD_RTCCLR |
271 //BIT_LDO_RF1_PD_RTCCLR |
272 BIT_LDO_RF0_PD_RTCCLR |
273 BIT_LDO_VDD25_PD_RTCCLR |
274 BIT_LDO_VDD28_PD_RTCCLR |
275 BIT_LDO_VDD18_PD_RTCCLR |
280 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET,
281 BIT_LDO_AVDD18_PD_RTCSET |
282 //BIT_DCDC_OTP_PD_RTCSET |
283 BIT_DCDC_WRF_PD_RTCSET |
284 //BIT_DCDC_GEN_PD_RTCSET |
285 //BIT_DCDC_MEM_PD_RTCSET |
286 //BIT_DCDC_ARM_PD_RTCSET |
287 //BIT_DCDC_CORE_PD_RTCSET|
288 //BIT_LDO_EMMCCORE_PD_RTCSET |
289 //BIT_LDO_EMMCIO_PD_RTCSET |
290 //BIT_LDO_RF2_PD_RTCSET |
291 BIT_LDO_RF1_PD_RTCSET |
292 //BIT_LDO_RF0_PD_RTCSET |
293 //BIT_LDO_VDD25_PD_RTCSET |
294 //BIT_LDO_VDD28_PD_RTCSET |
295 //BIT_LDO_VDD18_PD_RTCSET |
300 /**********************************************
301 * Following is AP LDO A DIE Sleep Control *
302 *********************************************/
303 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
305 BIT_SLP_DCDC_OTP_PD_EN |
306 //BIT_SLP_DCDCGEN_PD_EN |
307 BIT_SLP_DCDCWPA_PD_EN |
308 //BIT_SLP_DCDCWRF_PD_EN |
309 BIT_SLP_DCDCARM_PD_EN |
310 BIT_SLP_LDOEMMCCORE_PD_EN |
311 BIT_SLP_LDOEMMCIO_PD_EN |
312 BIT_SLP_LDORF2_PD_EN |
313 //BIT_SLP_LDORF1_PD_EN |
314 BIT_SLP_LDORF0_PD_EN |
315 BIT_SLP_LDOVDD25_PD_EN |
316 //BIT_SLP_LDOVDD28_PD_EN |
317 //BIT_SLP_LDOVDD18_PD_EN |
321 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
323 BIT_SLP_LDOLPREF_PD_EN |
324 BIT_SLP_LDOCLSG_PD_EN |
325 BIT_SLP_LDOUSB_PD_EN |
326 BIT_SLP_LDOCAMMOT_PD_EN |
327 BIT_SLP_LDOCAMIO_PD_EN |
328 BIT_SLP_LDOCAMD_PD_EN |
329 BIT_SLP_LDOCAMA_PD_EN |
330 BIT_SLP_LDOSIM2_PD_EN |
331 //BIT_SLP_LDOSIM1_PD_EN |
332 //BIT_SLP_LDOSIM0_PD_EN |
333 BIT_SLP_LDOSD_PD_EN |
334 BIT_SLP_LDOAVDD18_PD_EN |
338 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
339 //BIT_SLP_DCDC_BG_LP_EN |
340 //BIT_SLP_DCDCCORE_LP_EN |
341 //BIT_SLP_DCDCMEM_LP_EN |
342 //BIT_SLP_DCDCARM_LP_EN |
343 //BIT_SLP_DCDCGEN_LP_EN |
344 //BIT_SLP_DCDCWPA_LP_EN |
345 //BIT_SLP_DCDCWRF_LP_EN |
346 //BIT_SLP_LDOEMMCCORE_LP_EN |
347 //BIT_SLP_LDOEMMCIO_LP_EN |
348 //BIT_SLP_LDORF2_LP_EN |
349 //BIT_SLP_LDORF1_LP_EN |
350 //BIT_SLP_LDORF0_LP_EN |
354 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
356 //BIT_SLP_LDOVDD25_LP_EN |
357 //BIT_SLP_LDOVDD28_LP_EN |
358 //BIT_SLP_LDOVDD18_LP_EN |
359 //BIT_SLP_LDOCLSG_LP_EN |
360 //BIT_SLP_LDOUSB_LP_EN |
361 //BIT_SLP_LDOCAMMOT_LP_EN |
362 //BIT_SLP_LDOCAMIO_LP_EN |
363 //BIT_SLP_LDOCAMD_LP_EN |
364 //BIT_SLP_LDOCAMA_LP_EN |
365 //BIT_SLP_LDOSIM2_LP_EN |
366 //BIT_SLP_LDOSIM1_LP_EN |
367 //BIT_SLP_LDOSIM0_LP_EN |
368 //BIT_SLP_LDOSD_LP_EN |
369 //BIT_SLP_LDOAVDD18_LP_EN |
373 ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
374 BIT_SLP_XTLBUF_PD_EN |
380 ANA_REG_SET(ANA_REG_GLB_DDR2_CTRL,
382 BITS_DDR2_BUF_S_DS(0x0) |
383 BITS_DDR2_BUF_CHNS_DS(0x0) |
385 BITS_DDR2_BUF_S(0x3) |
386 BITS_DDR2_BUF_CHNS(0x0) |
390 /****************************************
391 * Following is CP LDO Sleep Control *
392 ****************************************/
394 ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
395 //BIT_LDO_VDD18_EXT_XTL2_EN |
396 //BIT_LDO_VDD18_EXT_XTL1_EN |
397 //BIT_LDO_VDD18_EXT_XTL0_EN |
398 //BIT_LDO_VDD18_XTL2_EN |
399 //BIT_LDO_VDD18_XTL1_EN |
400 //BIT_LDO_VDD18_XTL0_EN |
401 //BIT_LDO_VDD28_EXT_XTL2_EN |
402 //BIT_LDO_VDD28_EXT_XTL1_EN |
403 //BIT_LDO_VDD28_EXT_XTL0_EN |
404 //BIT_LDO_VDD28_XTL2_EN |
405 //BIT_LDO_VDD28_XTL1_EN |
406 //BIT_LDO_VDD28_XTL0_EN |
410 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
412 //BIT_LDO_RF1_EXT_XTL2_EN |
413 //BIT_LDO_RF1_EXT_XTL1_EN |
414 //BIT_LDO_RF1_EXT_XTL0_EN |
415 //BIT_LDO_RF1_XTL2_EN |
416 //BIT_LDO_RF1_XTL1_EN |
417 //BIT_LDO_RF1_XTL0_EN |
418 //BIT_LDO_RF0_EXT_XTL2_EN |
419 //BIT_LDO_RF0_EXT_XTL1_EN |
420 //BIT_LDO_RF0_EXT_XTL0_EN |
421 BIT_LDO_RF0_XTL2_EN |
422 BIT_LDO_RF0_XTL1_EN |
423 BIT_LDO_RF0_XTL0_EN |
427 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
428 //BIT_LDO_VDD25_EXT_XTL2_EN |
429 //BIT_LDO_VDD25_EXT_XTL1_EN |
430 //BIT_LDO_VDD25_EXT_XTL0_EN |
431 BIT_LDO_VDD25_XTL2_EN |
432 BIT_LDO_VDD25_XTL1_EN |
433 BIT_LDO_VDD25_XTL0_EN |
434 //BIT_LDO_RF2_EXT_XTL2_EN |
435 //BIT_LDO_RF2_EXT_XTL1_EN |
436 //BIT_LDO_RF2_EXT_XTL0_EN |
437 BIT_LDO_RF2_XTL2_EN |
438 BIT_LDO_RF2_XTL1_EN |
439 //BIT_LDO_RF2_XTL0_EN |
443 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
444 //BIT_LDO_AVDD18_EXT_XTL2_EN |
445 //BIT_LDO_AVDD18_EXT_XTL1_EN |
446 //BIT_LDO_AVDD18_EXT_XTL0_EN |
447 //BIT_LDO_AVDD18_XTL2_EN |
448 //BIT_LDO_AVDD18_XTL1_EN |
449 //BIT_LDO_AVDD18_XTL0_EN |
450 //BIT_LDO_SIM2_EXT_XTL2_EN |
451 //BIT_LDO_SIM2_EXT_XTL1_EN |
452 //BIT_LDO_SIM2_EXT_XTL0_EN |
453 //BIT_LDO_SIM2_XTL2_EN |
454 //BIT_LDO_SIM2_XTL1_EN |
455 //BIT_LDO_SIM2_XTL0_EN |
459 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
460 //BIT_DCDC_BG_EXT_XTL2_EN |
461 //BIT_DCDC_BG_EXT_XTL1_EN |
462 //BIT_DCDC_BG_EXT_XTL0_EN |
463 BIT_DCDC_BG_XTL2_EN |
464 BIT_DCDC_BG_XTL1_EN |
465 BIT_DCDC_BG_XTL0_EN |
466 //BIT_BG_EXT_XTL2_EN |
467 //BIT_BG_EXT_XTL1_EN |
468 //BIT_BG_EXT_XTL0_EN |
475 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
476 //BIT_DCDC_WRF_XTL2_EN |
477 //BIT_DCDC_WRF_XTL1_EN |
478 //BIT_DCDC_WRF_XTL0_EN |
479 BIT_DCDC_WPA_XTL2_EN |
480 //BIT_DCDC_WPA_XTL1_EN |
481 //BIT_DCDC_WPA_XTL0_EN |
482 BIT_DCDC_MEM_XTL2_EN |
483 BIT_DCDC_MEM_XTL1_EN |
484 BIT_DCDC_MEM_XTL0_EN |
485 BIT_DCDC_GEN_XTL2_EN |
486 BIT_DCDC_GEN_XTL1_EN |
487 BIT_DCDC_GEN_XTL0_EN |
488 BIT_DCDC_CORE_XTL2_EN |
489 BIT_DCDC_CORE_XTL1_EN |
490 BIT_DCDC_CORE_XTL0_EN |
494 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
495 //BIT_DCDC_WRF_EXT_XTL2_EN |
496 //BIT_DCDC_WRF_EXT_XTL1_EN |
497 //BIT_DCDC_WRF_EXT_XTL0_EN |
498 //BIT_DCDC_WPA_EXT_XTL2_EN |
499 //BIT_DCDC_WPA_EXT_XTL1_EN |
500 //BIT_DCDC_WPA_EXT_XTL0_EN |
501 //BIT_DCDC_MEM_EXT_XTL2_EN |
502 //BIT_DCDC_MEM_EXT_XTL1_EN |
503 //BIT_DCDC_MEM_EXT_XTL0_EN |
504 //BIT_DCDC_GEN_EXT_XTL2_EN |
505 //BIT_DCDC_GEN_EXT_XTL1_EN |
506 //BIT_DCDC_GEN_EXT_XTL0_EN |
507 //BIT_DCDC_CORE_EXT_XTL2_EN |
508 //BIT_DCDC_CORE_EXT_XTL1_EN |
509 //BIT_DCDC_CORE_EXT_XTL0_EN |
514 /************************************************
515 * Following is AP/CP LDO D DIE Sleep Control *
516 *************************************************/
518 CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
526 CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
534 CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
542 CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
543 BIT_XTLBUF0_CP2_SEL |
544 BIT_XTLBUF0_CP1_SEL |
545 BIT_XTLBUF0_CP0_SEL |
550 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
551 BIT_XTLBUF1_CP2_SEL |
552 BIT_XTLBUF1_CP1_SEL |
553 BIT_XTLBUF1_CP0_SEL |
558 CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
567 CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
575 /*caution tdpll & wpll sel config in spl*/
576 reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
584 CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
586 reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
594 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
596 CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
605 CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
606 BIT_WIFIPLL1_REF_SEL |
607 BIT_WIFIPLL1_CP2_SEL |
608 //BIT_WIFIPLL1_CP1_SEL |
609 //BIT_WIFIPLL1_CP0_SEL |
610 //BIT_WIFIPLL1_AP_SEL |
614 CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
615 BIT_WIFIPLL2_REF_SEL |
616 BIT_WIFIPLL2_CP2_SEL |
617 //BIT_WIFIPLL2_CP1_SEL |
618 //BIT_WIFIPLL2_CP0_SEL |
619 //BIT_WIFIPLL2_AP_SEL |
623 CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
624 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
625 BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
626 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
627 BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
631 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
632 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
633 BITS_PD_CA7_C0_PWR_ON_DLY(8) |
634 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
635 BITS_PD_CA7_C0_ISO_ON_DLY(2) |
639 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
640 BIT_PD_CA7_C1_FORCE_SHUTDOWN |
641 BITS_PD_CA7_C1_PWR_ON_DLY(8) |
642 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
643 BITS_PD_CA7_C1_ISO_ON_DLY(2) |
647 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
648 BIT_PD_CA7_C2_FORCE_SHUTDOWN |
649 BITS_PD_CA7_C2_PWR_ON_DLY(8) |
650 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
651 BITS_PD_CA7_C2_ISO_ON_DLY(2) |
655 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
656 BIT_PD_CA7_C3_FORCE_SHUTDOWN |
657 BITS_PD_CA7_C3_PWR_ON_DLY(8) |
658 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
659 BITS_PD_CA7_C3_ISO_ON_DLY(2) |
663 CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
664 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
665 BITS_PD_AP_SYS_PWR_ON_DLY(8) |
666 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
667 BITS_PD_AP_SYS_ISO_ON_DLY(6) |
671 CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
672 BIT_PD_MM_TOP_FORCE_SHUTDOWN |
673 BITS_PD_MM_TOP_PWR_ON_DLY(8) |
674 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
675 BITS_PD_MM_TOP_ISO_ON_DLY(4) |
679 CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
680 BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
681 BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
682 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
683 BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
687 CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
688 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
689 BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
690 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
691 BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
695 CHIP_REG_SET(REG_PMU_APB_PD_DDR_PUBL_CFG,
696 BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN |
697 BITS_PD_DDR_PUBL_PWR_ON_DLY(8) |
698 BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(0) |
699 BITS_PD_DDR_PUBL_ISO_ON_DLY(6) |
703 CHIP_REG_SET(REG_PMU_APB_PD_DDR_PHY_CFG,
704 BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN |
705 BITS_PD_DDR_PHY_PWR_ON_DLY(8) |
706 BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(0) |
707 BITS_PD_DDR_PHY_ISO_ON_DLY(6) |
711 CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
712 BITS_XTL1_WAIT_CNT(0x39) |
713 BITS_XTL0_WAIT_CNT(0x39) |
717 CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
718 BITS_XTLBUF1_WAIT_CNT(7) |
719 BITS_XTLBUF0_WAIT_CNT(7) |
723 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
724 BITS_WPLL_WAIT_CNT(7) |
725 BITS_TDPLL_WAIT_CNT(7) |
726 BITS_DPLL_WAIT_CNT(7) |
727 BITS_MPLL_WAIT_CNT(7) |
731 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
732 BITS_WIFIPLL2_WAIT_CNT(7) |
733 BITS_WIFIPLL1_WAIT_CNT(7) |
734 BITS_CPLL_WAIT_CNT(7) |
738 ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
739 BITS_SLP_IN_WAIT_DCDCARM(7) |
740 BITS_SLP_OUT_WAIT_DCDCARM(8) |
744 CHIP_REG_SET(REG_PMU_APB_PD_CODEC_TOP_CFG,
745 BIT_PD_CODEC_TOP_AUTO_SHUTDOWN_EN |
746 BITS_PD_CODEC_TOP_PWR_ON_DLY(8) |
747 BITS_PD_CODEC_TOP_PWR_ON_SEQ_DLY(0) |
748 BITS_PD_CODEC_TOP_ISO_ON_DLY(4) |
751 /*chip service package init*/
753 set_default_regulator();