1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
6 /***************************************************************************************************************************/
7 /* VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
8 /* AP x x v v v v v v v v v x v v v v v v v */
9 /* CP0 x x v v v x x x x v x x x x x x x x x */
10 /* CP1 x x v x x x x x x x x x x x x x x x x */
11 /* CP2 x x v v x v x x x v x x x x x x x x x */
12 /* EX0 x x x v x x x x x x x x x x x x x x x */
13 /* EX1 x x x x v x x x x x x x x x x x x x x */
14 /* EX2 x x x v x x x x x x x x x x x x x x x */
15 /***************************************************************************************************************************/
17 /***************************************************************************************************************************/
18 /* CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA LPGEN LPARM LPMEM LPCORE LPBG BG */
19 /* AP v v v v v v v v v v v x v v v v v v */
20 /* CP0 x x x x x x x x x x x x x x x x x x */
21 /* CP1 x x x x x x x x x x x x x x x x x x */
22 /* CP2 x x x x x x v v x x x x x x x x x x */
23 /* EX0 x x x x x x x x v x x x x x x x x x */
24 /* EX1 x x x x x x x x x x x x x x x x x x */
25 /* EX2 x x x x x x x x x x x x x x x x x x */
26 /***************************************************************************************************************************/
28 void init_ldo_sleep_gr(void)
31 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
32 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
34 //BIT_DCDC_TOPCLK6M_PD |
41 //BIT_LDO_EMMCCORE_PD |
51 ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
52 //BIT_LDO_LPREF_PD_SW |
68 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
70 BIT_SLP_DCDCRF_PD_EN |
71 BIT_SLP_DCDCCON_PD_EN |
72 //BIT_SLP_DCDCGEN_PD_EN |
73 BIT_SLP_DCDCWPA_PD_EN |
74 BIT_SLP_DCDCARM_PD_EN |
75 BIT_SLP_LDOVDD25_PD_EN |
76 BIT_SLP_LDORF0_PD_EN |
77 BIT_SLP_LDOEMMCCORE_PD_EN |
78 //BIT_SLP_LDOGEN0_PD_EN |
79 BIT_SLP_LDODCXO_PD_EN |
80 //BIT_SLP_LDOGEN1_PD_EN |
81 BIT_SLP_LDOWIFIPA_PD_EN |
82 //BIT_SLP_LDOVDD28_PD_EN |
83 //BIT_SLP_LDOVDD18_PD_EN |
86 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
88 BIT_SLP_LDOLPREF_PD_EN |
89 BIT_SLP_LDOSDCORE_PD_EN |
90 BIT_SLP_LDOUSB_PD_EN |
91 BIT_SLP_LDOCAMMOT_PD_EN |
92 BIT_SLP_LDOCAMIO_PD_EN |
93 BIT_SLP_LDOCAMD_PD_EN |
94 BIT_SLP_LDOCAMA_PD_EN |
95 BIT_SLP_LDOSIM2_PD_EN |
96 //BIT_SLP_LDOSIM1_PD_EN |
97 //BIT_SLP_LDOSIM0_PD_EN |
98 BIT_SLP_LDOSDIO_PD_EN |
101 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
102 //BIT_SLP_DCDCRF_LP_EN |
103 //BIT_SLP_DCDCCON_LP_EN |
104 //BIT_SLP_DCDCCORE_LP_EN |
105 //BIT_SLP_DCDCMEM_LP_EN |
106 //BIT_SLP_DCDCARM_LP_EN |
107 //BIT_SLP_DCDCGEN_LP_EN |
108 //BIT_SLP_DCDCWPA_LP_EN |
109 //BIT_SLP_LDORF0_LP_EN |
110 //BIT_SLP_LDOEMMCCORE_LP_EN |
111 //BIT_SLP_LDOGEN0_LP_EN |
112 //BIT_SLP_LDODCXO_LP_EN |
113 //BIT_SLP_LDOGEN1_LP_EN |
114 //BIT_SLP_LDOWIFIPA_LP_EN |
115 //BIT_SLP_LDOVDD28_LP_EN |
116 //BIT_SLP_LDOVDD18_LP_EN |
119 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
121 //BIT_LDOVDD25_LP_EN_SW |
122 //BIT_LDOSDCORE_LP_EN_SW |
123 //BIT_LDOUSB_LP_EN_SW |
124 //BIT_SLP_LDOVDD25_LP_EN |
125 //BIT_SLP_LDOSDCORE_LP_EN |
126 //BIT_SLP_LDOUSB_LP_EN |
127 //BIT_SLP_LDOCAMMOT_LP_EN |
128 //BIT_SLP_LDOCAMIO_LP_EN |
129 //BIT_SLP_LDOCAMD_LP_EN |
130 //BIT_SLP_LDOCAMA_LP_EN |
131 //BIT_SLP_LDOSIM2_LP_EN |
132 //BIT_SLP_LDOSIM1_LP_EN |
133 //BIT_SLP_LDOSIM0_LP_EN |
134 //BIT_SLP_LDOSDIO_LP_EN |
137 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
138 //BIT_LDOCAMIO_LP_EN_SW |
139 //BIT_LDOCAMMOT_LP_EN_SW |
140 //BIT_LDOCAMD_LP_EN_SW |
141 //BIT_LDOCAMA_LP_EN_SW |
142 //BIT_LDOSIM2_LP_EN_SW |
143 //BIT_LDOSIM1_LP_EN_SW |
144 //BIT_LDOSIM0_LP_EN_SW |
145 //BIT_LDOSDIO_LP_EN_SW |
146 //BIT_LDORF0_LP_EN_SW |
147 //BIT_LDOEMMCCORE_LP_EN_SW |
148 //BIT_LDOGEN0_LP_EN_SW |
149 //BIT_LDODCXO_LP_EN_SW |
150 //BIT_LDOGEN1_LP_EN_SW |
151 //BIT_LDOWIFIPA_LP_EN_SW |
152 //BIT_LDOVDD28_LP_EN_SW |
153 //BIT_LDOVDD18_LP_EN_SW |
156 ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
157 BIT_SLP_XTLBUF_PD_EN |
159 BITS_XTL_WAIT(0x32) |
163 /****************************************
164 * Following is CP LDO Sleep Control *
165 ****************************************/
166 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
168 //BIT_LDO_GEN0_EXT_XTL0_EN |
169 //BIT_LDO_GEN0_XTL1_EN |
170 //BIT_LDO_GEN0_XTL0_EN |
171 //BIT_LDO_GEN1_EXT_XTL0_EN |
172 //BIT_LDO_GEN1_XTL1_EN |
173 //BIT_LDO_GEN1_XTL0_EN |
174 BIT_LDO_DCXO_EXT_XTL0_EN |
175 BIT_LDO_DCXO_XTL1_EN |
176 BIT_LDO_DCXO_XTL0_EN |
177 //BIT_LDO_VDD18_EXT_XTL0_EN |
178 //BIT_LDO_VDD18_XTL1_EN |
179 //BIT_LDO_VDD18_XTL0_EN |
180 //BIT_LDO_VDD28_EXT_XTL0_EN |
181 //BIT_LDO_VDD28_XTL1_EN |
182 //BIT_LDO_VDD28_XTL0_EN |
185 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
186 BIT_LDO_RF0_EXT_XTL0_EN |
187 BIT_LDO_RF0_XTL1_EN |
188 BIT_LDO_RF0_XTL0_EN |
189 BIT_LDO_WIFIPA_EXT_XTL0_EN |
190 BIT_LDO_WIFIPA_XTL1_EN |
191 BIT_LDO_WIFIPA_XTL0_EN |
192 BIT_LDO_SIM2_EXT_XTL0_EN |
193 BIT_LDO_SIM2_XTL1_EN |
194 BIT_LDO_SIM2_XTL0_EN |
195 BIT_LDO_SIM1_EXT_XTL0_EN |
196 BIT_LDO_SIM1_XTL1_EN |
197 BIT_LDO_SIM1_XTL0_EN |
198 BIT_LDO_SIM0_EXT_XTL0_EN |
199 BIT_LDO_SIM0_XTL1_EN |
200 BIT_LDO_SIM0_XTL0_EN |
203 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
204 BIT_LDO_VDD25_EXT_XTL0_EN |
205 BIT_LDO_VDD25_XTL1_EN |
206 BIT_LDO_VDD25_XTL0_EN |
207 BIT_DCDC_RF_EXT_XTL0_EN |
208 BIT_DCDC_RF_XTL1_EN |
209 BIT_DCDC_RF_XTL0_EN |
218 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
219 BIT_DCDC_CON_EXT_XTL0_EN |
220 BIT_DCDC_CON_XTL1_EN |
221 BIT_DCDC_CON_XTL0_EN |
222 BIT_DCDC_WPA_EXT_XTL0_EN |
223 BIT_DCDC_WPA_XTL1_EN |
224 BIT_DCDC_WPA_XTL0_EN |
225 BIT_DCDC_MEM_EXT_XTL0_EN |
226 BIT_DCDC_MEM_XTL1_EN |
227 BIT_DCDC_MEM_XTL0_EN |
228 BIT_DCDC_GEN_EXT_XTL0_EN |
229 BIT_DCDC_GEN_XTL1_EN |
230 BIT_DCDC_GEN_XTL0_EN |
231 BIT_DCDC_CORE_EXT_XTL0_EN |
232 BIT_DCDC_CORE_XTL1_EN |
233 BIT_DCDC_CORE_XTL0_EN |
237 /*add by sam.sun, vddsim2 value 2.8v, bit15~bit8:a0*/
238 ANA_REG_SET(ANA_REG_GLB_LDO_V_CTRL5,
239 BITS_LDO_SIM2_V(0xa0) |
244 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR,
245 //BIT_LDO_AVDD18_PD_RTCCLR |
246 BIT_DCDC_OTP_PD_RTCCLR |
247 //BIT_DCDC_WRF_PD_RTCCLR |
248 BIT_DCDC_GEN_PD_RTCCLR |
249 BIT_DCDC_MEM_PD_RTCCLR |
250 BIT_DCDC_ARM_PD_RTCCLR |
251 BIT_DCDC_CORE_PD_RTCCLR|
252 BIT_LDO_EMMCCORE_PD_RTCCLR |
253 BIT_LDO_EMMCIO_PD_RTCCLR |
254 BIT_LDO_RF2_PD_RTCCLR |
255 //BIT_LDO_RF1_PD_RTCCLR |
256 BIT_LDO_RF0_PD_RTCCLR |
257 BIT_LDO_VDD25_PD_RTCCLR |
258 BIT_LDO_VDD28_PD_RTCCLR |
259 BIT_LDO_VDD18_PD_RTCCLR |
264 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET,
265 BIT_LDO_AVDD18_PD_RTCSET |
266 //BIT_DCDC_OTP_PD_RTCSET |
267 BIT_DCDC_WRF_PD_RTCSET |
268 //BIT_DCDC_GEN_PD_RTCSET |
269 //BIT_DCDC_MEM_PD_RTCSET |
270 //BIT_DCDC_ARM_PD_RTCSET |
271 //BIT_DCDC_CORE_PD_RTCSET|
272 //BIT_LDO_EMMCCORE_PD_RTCSET |
273 //BIT_LDO_EMMCIO_PD_RTCSET |
274 //BIT_LDO_RF2_PD_RTCSET |
275 BIT_LDO_RF1_PD_RTCSET |
276 //BIT_LDO_RF0_PD_RTCSET |
277 //BIT_LDO_VDD25_PD_RTCSET |
278 //BIT_LDO_VDD28_PD_RTCSET |
279 //BIT_LDO_VDD18_PD_RTCSET |
284 /**********************************************
285 * Following is AP LDO A DIE Sleep Control *
286 *********************************************/
287 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
289 BIT_SLP_DCDC_OTP_PD_EN |
290 //BIT_SLP_DCDCGEN_PD_EN |
291 BIT_SLP_DCDCWPA_PD_EN |
292 //BIT_SLP_DCDCWRF_PD_EN |
293 BIT_SLP_DCDCARM_PD_EN |
294 BIT_SLP_LDOEMMCCORE_PD_EN |
295 BIT_SLP_LDOEMMCIO_PD_EN |
296 BIT_SLP_LDORF2_PD_EN |
297 //BIT_SLP_LDORF1_PD_EN |
298 BIT_SLP_LDORF0_PD_EN |
299 BIT_SLP_LDOVDD25_PD_EN |
300 //BIT_SLP_LDOVDD28_PD_EN |
301 //BIT_SLP_LDOVDD18_PD_EN |
305 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
307 BIT_SLP_LDOLPREF_PD_EN |
308 BIT_SLP_LDOCLSG_PD_EN |
309 BIT_SLP_LDOUSB_PD_EN |
310 BIT_SLP_LDOCAMMOT_PD_EN |
311 BIT_SLP_LDOCAMIO_PD_EN |
312 BIT_SLP_LDOCAMD_PD_EN |
313 BIT_SLP_LDOCAMA_PD_EN |
314 BIT_SLP_LDOSIM2_PD_EN |
315 //BIT_SLP_LDOSIM1_PD_EN |
316 //BIT_SLP_LDOSIM0_PD_EN |
317 BIT_SLP_LDOSD_PD_EN |
318 BIT_SLP_LDOAVDD18_PD_EN |
322 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
323 //BIT_SLP_DCDC_BG_LP_EN |
324 //BIT_SLP_DCDCCORE_LP_EN |
325 //BIT_SLP_DCDCMEM_LP_EN |
326 //BIT_SLP_DCDCARM_LP_EN |
327 //BIT_SLP_DCDCGEN_LP_EN |
328 //BIT_SLP_DCDCWPA_LP_EN |
329 //BIT_SLP_DCDCWRF_LP_EN |
330 //BIT_SLP_LDOEMMCCORE_LP_EN |
331 //BIT_SLP_LDOEMMCIO_LP_EN |
332 //BIT_SLP_LDORF2_LP_EN |
333 //BIT_SLP_LDORF1_LP_EN |
334 //BIT_SLP_LDORF0_LP_EN |
338 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
340 //BIT_SLP_LDOVDD25_LP_EN |
341 //BIT_SLP_LDOVDD28_LP_EN |
342 //BIT_SLP_LDOVDD18_LP_EN |
343 //BIT_SLP_LDOCLSG_LP_EN |
344 //BIT_SLP_LDOUSB_LP_EN |
345 //BIT_SLP_LDOCAMMOT_LP_EN |
346 //BIT_SLP_LDOCAMIO_LP_EN |
347 //BIT_SLP_LDOCAMD_LP_EN |
348 //BIT_SLP_LDOCAMA_LP_EN |
349 //BIT_SLP_LDOSIM2_LP_EN |
350 //BIT_SLP_LDOSIM1_LP_EN |
351 //BIT_SLP_LDOSIM0_LP_EN |
352 //BIT_SLP_LDOSD_LP_EN |
353 //BIT_SLP_LDOAVDD18_LP_EN |
357 ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
358 BIT_SLP_XTLBUF_PD_EN |
364 ANA_REG_SET(ANA_REG_GLB_DDR2_CTRL,
366 BITS_DDR2_BUF_S_DS(0x0) |
367 BITS_DDR2_BUF_CHNS_DS(0x0) |
369 BITS_DDR2_BUF_S(0x3) |
370 BITS_DDR2_BUF_CHNS(0x0) |
374 /****************************************
375 * Following is CP LDO Sleep Control *
376 ****************************************/
378 ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
379 //BIT_LDO_VDD18_EXT_XTL2_EN |
380 //BIT_LDO_VDD18_EXT_XTL1_EN |
381 //BIT_LDO_VDD18_EXT_XTL0_EN |
382 //BIT_LDO_VDD18_XTL2_EN |
383 //BIT_LDO_VDD18_XTL1_EN |
384 //BIT_LDO_VDD18_XTL0_EN |
385 //BIT_LDO_VDD28_EXT_XTL2_EN |
386 //BIT_LDO_VDD28_EXT_XTL1_EN |
387 //BIT_LDO_VDD28_EXT_XTL0_EN |
388 //BIT_LDO_VDD28_XTL2_EN |
389 //BIT_LDO_VDD28_XTL1_EN |
390 //BIT_LDO_VDD28_XTL0_EN |
394 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
396 //BIT_LDO_RF1_EXT_XTL2_EN |
397 //BIT_LDO_RF1_EXT_XTL1_EN |
398 //BIT_LDO_RF1_EXT_XTL0_EN |
399 //BIT_LDO_RF1_XTL2_EN |
400 //BIT_LDO_RF1_XTL1_EN |
401 //BIT_LDO_RF1_XTL0_EN |
402 //BIT_LDO_RF0_EXT_XTL2_EN |
403 //BIT_LDO_RF0_EXT_XTL1_EN |
404 //BIT_LDO_RF0_EXT_XTL0_EN |
405 BIT_LDO_RF0_XTL2_EN |
406 BIT_LDO_RF0_XTL1_EN |
407 BIT_LDO_RF0_XTL0_EN |
411 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
412 //BIT_LDO_VDD25_EXT_XTL2_EN |
413 //BIT_LDO_VDD25_EXT_XTL1_EN |
414 //BIT_LDO_VDD25_EXT_XTL0_EN |
415 BIT_LDO_VDD25_XTL2_EN |
416 BIT_LDO_VDD25_XTL1_EN |
417 BIT_LDO_VDD25_XTL0_EN |
418 //BIT_LDO_RF2_EXT_XTL2_EN |
419 //BIT_LDO_RF2_EXT_XTL1_EN |
420 //BIT_LDO_RF2_EXT_XTL0_EN |
421 BIT_LDO_RF2_XTL2_EN |
422 BIT_LDO_RF2_XTL1_EN |
423 //BIT_LDO_RF2_XTL0_EN |
427 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
428 //BIT_LDO_AVDD18_EXT_XTL2_EN |
429 //BIT_LDO_AVDD18_EXT_XTL1_EN |
430 //BIT_LDO_AVDD18_EXT_XTL0_EN |
431 //BIT_LDO_AVDD18_XTL2_EN |
432 //BIT_LDO_AVDD18_XTL1_EN |
433 //BIT_LDO_AVDD18_XTL0_EN |
434 //BIT_LDO_SIM2_EXT_XTL2_EN |
435 //BIT_LDO_SIM2_EXT_XTL1_EN |
436 //BIT_LDO_SIM2_EXT_XTL0_EN |
437 //BIT_LDO_SIM2_XTL2_EN |
438 //BIT_LDO_SIM2_XTL1_EN |
439 //BIT_LDO_SIM2_XTL0_EN |
443 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
444 //BIT_DCDC_BG_EXT_XTL2_EN |
445 //BIT_DCDC_BG_EXT_XTL1_EN |
446 //BIT_DCDC_BG_EXT_XTL0_EN |
447 BIT_DCDC_BG_XTL2_EN |
448 BIT_DCDC_BG_XTL1_EN |
449 BIT_DCDC_BG_XTL0_EN |
450 //BIT_BG_EXT_XTL2_EN |
451 //BIT_BG_EXT_XTL1_EN |
452 //BIT_BG_EXT_XTL0_EN |
459 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
460 //BIT_DCDC_WRF_XTL2_EN |
461 //BIT_DCDC_WRF_XTL1_EN |
462 //BIT_DCDC_WRF_XTL0_EN |
463 BIT_DCDC_WPA_XTL2_EN |
464 //BIT_DCDC_WPA_XTL1_EN |
465 //BIT_DCDC_WPA_XTL0_EN |
466 BIT_DCDC_MEM_XTL2_EN |
467 BIT_DCDC_MEM_XTL1_EN |
468 BIT_DCDC_MEM_XTL0_EN |
469 BIT_DCDC_GEN_XTL2_EN |
470 BIT_DCDC_GEN_XTL1_EN |
471 BIT_DCDC_GEN_XTL0_EN |
472 BIT_DCDC_CORE_XTL2_EN |
473 BIT_DCDC_CORE_XTL1_EN |
474 BIT_DCDC_CORE_XTL0_EN |
478 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
479 //BIT_DCDC_WRF_EXT_XTL2_EN |
480 //BIT_DCDC_WRF_EXT_XTL1_EN |
481 //BIT_DCDC_WRF_EXT_XTL0_EN |
482 //BIT_DCDC_WPA_EXT_XTL2_EN |
483 //BIT_DCDC_WPA_EXT_XTL1_EN |
484 //BIT_DCDC_WPA_EXT_XTL0_EN |
485 //BIT_DCDC_MEM_EXT_XTL2_EN |
486 //BIT_DCDC_MEM_EXT_XTL1_EN |
487 //BIT_DCDC_MEM_EXT_XTL0_EN |
488 //BIT_DCDC_GEN_EXT_XTL2_EN |
489 //BIT_DCDC_GEN_EXT_XTL1_EN |
490 //BIT_DCDC_GEN_EXT_XTL0_EN |
491 //BIT_DCDC_CORE_EXT_XTL2_EN |
492 //BIT_DCDC_CORE_EXT_XTL1_EN |
493 //BIT_DCDC_CORE_EXT_XTL0_EN |
498 /************************************************
499 * Following is AP/CP LDO D DIE Sleep Control *
500 *************************************************/
502 CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
510 CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
518 CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
526 CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
527 BIT_XTLBUF0_CP2_SEL |
528 BIT_XTLBUF0_CP1_SEL |
529 BIT_XTLBUF0_CP0_SEL |
534 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
535 BIT_XTLBUF1_CP2_SEL |
536 BIT_XTLBUF1_CP1_SEL |
537 BIT_XTLBUF1_CP0_SEL |
542 CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
551 CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
559 /*caution tdpll & wpll sel config in spl*/
560 reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
568 CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
570 reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
578 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
580 CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
589 CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
590 BIT_WIFIPLL1_REF_SEL |
591 BIT_WIFIPLL1_CP2_SEL |
592 //BIT_WIFIPLL1_CP1_SEL |
593 //BIT_WIFIPLL1_CP0_SEL |
594 //BIT_WIFIPLL1_AP_SEL |
598 CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
599 BIT_WIFIPLL2_REF_SEL |
600 BIT_WIFIPLL2_CP2_SEL |
601 //BIT_WIFIPLL2_CP1_SEL |
602 //BIT_WIFIPLL2_CP0_SEL |
603 //BIT_WIFIPLL2_AP_SEL |
607 CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
608 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
609 BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
610 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
611 BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
615 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
616 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
617 BITS_PD_CA7_C0_PWR_ON_DLY(8) |
618 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
619 BITS_PD_CA7_C0_ISO_ON_DLY(2) |
623 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
624 BIT_PD_CA7_C1_FORCE_SHUTDOWN |
625 BITS_PD_CA7_C1_PWR_ON_DLY(8) |
626 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
627 BITS_PD_CA7_C1_ISO_ON_DLY(2) |
631 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
632 BIT_PD_CA7_C2_FORCE_SHUTDOWN |
633 BITS_PD_CA7_C2_PWR_ON_DLY(8) |
634 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
635 BITS_PD_CA7_C2_ISO_ON_DLY(2) |
639 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
640 BIT_PD_CA7_C3_FORCE_SHUTDOWN |
641 BITS_PD_CA7_C3_PWR_ON_DLY(8) |
642 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
643 BITS_PD_CA7_C3_ISO_ON_DLY(2) |
647 CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
648 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
649 BITS_PD_AP_SYS_PWR_ON_DLY(8) |
650 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
651 BITS_PD_AP_SYS_ISO_ON_DLY(6) |
655 CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
656 BIT_PD_MM_TOP_FORCE_SHUTDOWN |
657 BITS_PD_MM_TOP_PWR_ON_DLY(8) |
658 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
659 BITS_PD_MM_TOP_ISO_ON_DLY(4) |
663 CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
664 BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
665 BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
666 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
667 BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
671 CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
672 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
673 BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
674 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
675 BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
679 CHIP_REG_SET(REG_PMU_APB_PD_DDR_PUBL_CFG,
680 BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN |
681 BITS_PD_DDR_PUBL_PWR_ON_DLY(8) |
682 BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(0) |
683 BITS_PD_DDR_PUBL_ISO_ON_DLY(6) |
687 CHIP_REG_SET(REG_PMU_APB_PD_DDR_PHY_CFG,
688 BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN |
689 BITS_PD_DDR_PHY_PWR_ON_DLY(8) |
690 BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(0) |
691 BITS_PD_DDR_PHY_ISO_ON_DLY(6) |
695 CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
696 BITS_XTL1_WAIT_CNT(0x39) |
697 BITS_XTL0_WAIT_CNT(0x39) |
701 CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
702 BITS_XTLBUF1_WAIT_CNT(7) |
703 BITS_XTLBUF0_WAIT_CNT(7) |
707 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
708 BITS_WPLL_WAIT_CNT(7) |
709 BITS_TDPLL_WAIT_CNT(7) |
710 BITS_DPLL_WAIT_CNT(7) |
711 BITS_MPLL_WAIT_CNT(7) |
715 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
716 BITS_WIFIPLL2_WAIT_CNT(7) |
717 BITS_WIFIPLL1_WAIT_CNT(7) |
718 BITS_CPLL_WAIT_CNT(7) |
722 ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
723 BITS_SLP_IN_WAIT_DCDCARM(7) |
724 BITS_SLP_OUT_WAIT_DCDCARM(8) |
727 /*chip service package init*/