1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
6 /***************************************************************************************************************************/
7 /* VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
8 /* AP x x v v v v v v v v v x v v v v v v v */
9 /* CP0 x x v v v x x x x v x x x x x x x x x */
10 /* CP1 x x v x x x x x x x x x x x x x x x x */
11 /* CP2 x x v v x v x x x v x x x x x x x x x */
12 /* EX0 x x x v x x x x x x x x x x x x x x x */
13 /* EX1 x x x x v x x x x x x x x x x x x x x */
14 /* EX2 x x x v x x x x x x x x x x x x x x x */
15 /***************************************************************************************************************************/
17 /***************************************************************************************************************************/
18 /* CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA LPGEN LPARM LPMEM LPCORE LPBG BG */
19 /* AP v v v v v v v v v v v x v v v v v v */
20 /* CP0 x x x x x x x x x x x x x x x x x x */
21 /* CP1 x x x x x x x x x x x x x x x x x x */
22 /* CP2 x x x x x x v v x x x x x x x x x x */
23 /* EX0 x x x x x x x x v x x x x x x x x x */
24 /* EX1 x x x x x x x x x x x x x x x x x x */
25 /* EX2 x x x x x x x x x x x x x x x x x x */
26 /***************************************************************************************************************************/
27 int set_default_regulator(void);
28 void init_ldo_sleep_gr(void)
32 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x6e7f);
33 while( (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & 0x8000) != 0x8000 );
35 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
36 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
38 //BIT_DCDC_TOPCLK6M_PD |
45 //BIT_LDO_EMMCCORE_PD |
55 ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
56 //BIT_LDO_LPREF_PD_SW |
73 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,0x0000);
75 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
77 BIT_SLP_DCDCRF_PD_EN |
78 BIT_SLP_DCDCCON_PD_EN |
79 //BIT_SLP_DCDCGEN_PD_EN |
80 //BIT_SLP_DCDCWPA_PD_EN |
81 BIT_SLP_DCDCARM_PD_EN |
82 BIT_SLP_LDOVDD25_PD_EN |
83 BIT_SLP_LDORF0_PD_EN |
84 BIT_SLP_LDOEMMCCORE_PD_EN |
85 BIT_SLP_LDOGEN0_PD_EN |
86 BIT_SLP_LDODCXO_PD_EN |
87 //BIT_SLP_LDOGEN1_PD_EN |
88 BIT_SLP_LDOWIFIPA_PD_EN |
89 //BIT_SLP_LDOVDD28_PD_EN |
90 //BIT_SLP_LDOVDD18_PD_EN |
93 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
95 BIT_SLP_LDOLPREF_PD_EN |
96 BIT_SLP_LDOSDCORE_PD_EN |
97 BIT_SLP_LDOUSB_PD_EN |
98 BIT_SLP_LDOCAMMOT_PD_EN |
99 BIT_SLP_LDOCAMIO_PD_EN |
100 BIT_SLP_LDOCAMD_PD_EN |
101 BIT_SLP_LDOCAMA_PD_EN |
102 //BIT_SLP_LDOSIM2_PD_EN |
103 //BIT_SLP_LDOSIM1_PD_EN |
104 //BIT_SLP_LDOSIM0_PD_EN |
105 BIT_SLP_LDOSDIO_PD_EN |
108 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
109 //BIT_SLP_DCDCRF_LP_EN |
110 //BIT_SLP_DCDCCON_LP_EN |
111 BIT_SLP_DCDCCORE_LP_EN |
112 BIT_SLP_DCDCMEM_LP_EN |
113 //BIT_SLP_DCDCARM_LP_EN |
114 BIT_SLP_DCDCGEN_LP_EN |
115 //BIT_SLP_DCDCWPA_LP_EN |
116 //BIT_SLP_LDORF0_LP_EN |
117 //BIT_SLP_LDOEMMCCORE_LP_EN |
118 //BIT_SLP_LDOGEN0_LP_EN |
119 //BIT_SLP_LDODCXO_LP_EN |
120 //BIT_SLP_LDOGEN1_LP_EN |
121 //BIT_SLP_LDOWIFIPA_LP_EN |
122 //BIT_SLP_LDOVDD28_LP_EN |
123 //BIT_SLP_LDOVDD18_LP_EN |
126 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
128 //BIT_LDOVDD25_LP_EN_SW |
129 //BIT_LDOSDCORE_LP_EN_SW |
130 //BIT_LDOUSB_LP_EN_SW |
131 //BIT_SLP_LDOVDD25_LP_EN |
132 //BIT_SLP_LDOSDCORE_LP_EN |
133 //BIT_SLP_LDOUSB_LP_EN |
134 //BIT_SLP_LDOCAMMOT_LP_EN |
135 //BIT_SLP_LDOCAMIO_LP_EN |
136 //BIT_SLP_LDOCAMD_LP_EN |
137 //BIT_SLP_LDOCAMA_LP_EN |
138 //BIT_SLP_LDOSIM2_LP_EN |
139 //BIT_SLP_LDOSIM1_LP_EN |
140 //BIT_SLP_LDOSIM0_LP_EN |
141 //BIT_SLP_LDOSDIO_LP_EN |
144 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
145 //BIT_LDOCAMIO_LP_EN_SW |
146 //BIT_LDOCAMMOT_LP_EN_SW |
147 //BIT_LDOCAMD_LP_EN_SW |
148 //BIT_LDOCAMA_LP_EN_SW |
149 //BIT_LDOSIM2_LP_EN_SW |
150 //BIT_LDOSIM1_LP_EN_SW |
151 //BIT_LDOSIM0_LP_EN_SW |
152 //BIT_LDOSDIO_LP_EN_SW |
153 //BIT_LDORF0_LP_EN_SW |
154 //BIT_LDOEMMCCORE_LP_EN_SW |
155 //BIT_LDOGEN0_LP_EN_SW |
156 //BIT_LDODCXO_LP_EN_SW |
157 //BIT_LDOGEN1_LP_EN_SW |
158 //BIT_LDOWIFIPA_LP_EN_SW |
159 //BIT_LDOVDD28_LP_EN_SW |
160 //BIT_LDOVDD18_LP_EN_SW |
163 ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
164 BIT_SLP_XTLBUF_PD_EN |
166 BITS_XTL_WAIT(0x32) |
170 /****************************************
171 * Following is CP LDO Sleep Control *
172 ****************************************/
173 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
175 //BIT_LDO_GEN0_EXT_XTL0_EN |
176 //BIT_LDO_GEN0_XTL1_EN |
177 //BIT_LDO_GEN0_XTL0_EN |
178 //BIT_LDO_GEN1_EXT_XTL0_EN |
179 //BIT_LDO_GEN1_XTL1_EN |
180 //BIT_LDO_GEN1_XTL0_EN |
181 BIT_LDO_DCXO_EXT_XTL0_EN |
182 BIT_LDO_DCXO_XTL1_EN |
183 BIT_LDO_DCXO_XTL0_EN |
184 //BIT_LDO_VDD18_EXT_XTL0_EN |
185 //BIT_LDO_VDD18_XTL1_EN |
186 //BIT_LDO_VDD18_XTL0_EN |
187 //BIT_LDO_VDD28_EXT_XTL0_EN |
188 //BIT_LDO_VDD28_XTL1_EN |
189 //BIT_LDO_VDD28_XTL0_EN |
192 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
193 BIT_LDO_RF0_EXT_XTL0_EN |
194 BIT_LDO_RF0_XTL1_EN |
195 BIT_LDO_RF0_XTL0_EN |
196 BIT_LDO_WIFIPA_EXT_XTL0_EN |
197 BIT_LDO_WIFIPA_XTL1_EN |
198 BIT_LDO_WIFIPA_XTL0_EN |
199 //BIT_LDO_SIM2_EXT_XTL0_EN |
200 //BIT_LDO_SIM2_XTL1_EN |
201 //BIT_LDO_SIM2_XTL0_EN |
202 //BIT_LDO_SIM1_EXT_XTL0_EN |
203 //BIT_LDO_SIM1_XTL1_EN |
204 //BIT_LDO_SIM1_XTL0_EN |
205 //BIT_LDO_SIM0_EXT_XTL0_EN |
206 //BIT_LDO_SIM0_XTL1_EN |
207 //BIT_LDO_SIM0_XTL0_EN |
210 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
211 BIT_LDO_VDD25_EXT_XTL0_EN |
212 BIT_LDO_VDD25_XTL1_EN |
213 BIT_LDO_VDD25_XTL0_EN |
214 BIT_DCDC_RF_EXT_XTL0_EN |
215 BIT_DCDC_RF_XTL1_EN |
216 BIT_DCDC_RF_XTL0_EN |
225 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
226 BIT_DCDC_CON_EXT_XTL0_EN |
227 BIT_DCDC_CON_XTL1_EN |
228 BIT_DCDC_CON_XTL0_EN |
229 //BIT_DCDC_WPA_EXT_XTL0_EN |
230 //BIT_DCDC_WPA_XTL1_EN |
231 //BIT_DCDC_WPA_XTL0_EN |
232 BIT_DCDC_MEM_EXT_XTL0_EN |
233 BIT_DCDC_MEM_XTL1_EN |
234 BIT_DCDC_MEM_XTL0_EN |
235 BIT_DCDC_GEN_EXT_XTL0_EN |
236 BIT_DCDC_GEN_XTL1_EN |
237 BIT_DCDC_GEN_XTL0_EN |
238 BIT_DCDC_CORE_EXT_XTL0_EN |
239 BIT_DCDC_CORE_XTL1_EN |
240 BIT_DCDC_CORE_XTL0_EN |
244 /*add by sam.sun, vddsim2 value 2.8v, bit15~bit8:a0*/
245 ANA_REG_SET(ANA_REG_GLB_LDO_V_CTRL5,
246 BITS_LDO_SIM2_V(0xa0) |
250 /************************************************
251 * Following is AP/CP LDO D DIE Sleep Control *
252 *************************************************/
254 CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
262 CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
270 CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
278 CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
279 BIT_XTLBUF0_CP2_SEL |
280 BIT_XTLBUF0_CP1_SEL |
281 BIT_XTLBUF0_CP0_SEL |
286 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
287 BIT_XTLBUF1_CP2_SEL |
288 BIT_XTLBUF1_CP1_SEL |
289 BIT_XTLBUF1_CP0_SEL |
294 CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
303 CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
311 /*caution tdpll & wpll sel config in spl*/
312 reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
320 CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
322 reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
330 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
332 CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
341 CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
342 //BIT_WIFIPLL1_REF_SEL |
343 BIT_WIFIPLL1_CP2_SEL |
344 //BIT_WIFIPLL1_CP1_SEL |
345 //BIT_WIFIPLL1_CP0_SEL |
346 //BIT_WIFIPLL1_AP_SEL |
350 CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
351 //BIT_WIFIPLL2_REF_SEL |
352 BIT_WIFIPLL2_CP2_SEL |
353 //BIT_WIFIPLL2_CP1_SEL |
354 //BIT_WIFIPLL2_CP0_SEL |
355 //BIT_WIFIPLL2_AP_SEL |
359 /*chip service package init*/
364 int init_ldo_voltage(void)
366 regulator_set_voltage("vddgen",2100);