board/spreadtrum/sp7715ea/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27
  28 void init_ldo_sleep_gr(void)
  29 {
  30         u32 reg_val;
  31
  32         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0x6e7f));
  33
  34         do{
  35                 reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT);
  36         }while(reg_val == 0);
  37
  38         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
  39         BIT_DCDC_TOP_CLKF_EN|
  40         BIT_DCDC_TOP_OSC_EN|
  41         //BIT_DCDC_GEN_PD|
  42         //BIT_DCDC_MEM_PD|
  43         //BIT_DCDC_ARM_PD|
  44         //BIT_DCDC_CORE_PD|
  45         //BIT_LDO_RF0_PD|
  46         //BIT_LDO_EMMCCORE_PD|
  47         //BIT_LDO_EMMCIO_PD|
  48         BIT_LDO_DCXO_PD|
  49         //BIT_LDO_CON_PD|
  50         //BIT_LDO_VDD25_PD|
  51         //BIT_LDO_VDD28_PD|
  52         //BIT_LDO_VDD18_PD|
  53         //BIT_BG_PD|
  54         0
  55         );
  56
  57         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0));
  58
  59         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0);
  60         reg_val &= ~BITS_DCDC_CORE_CTL_DS_SW(7);
  61         reg_val |= BITS_DCDC_CORE_CTL_DS_SW(4);
  62         ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL0,reg_val);
  63
  64         /**********************************************
  65          *   Following is AP LDO A DIE Sleep Control  *
  66          *********************************************/
  67         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  68         BIT_SLP_IO_EN |
  69         //BIT_SLP_DCDCGEN_PD_EN |
  70         BIT_SLP_DCDCWPA_PD_EN |
  71         BIT_SLP_DCDCARM_PD_EN |
  72         BIT_SLP_LDORF0_PD_EN |
  73         BIT_SLP_LDOEMMCCORE_PD_EN |
  74         BIT_SLP_LDOEMMCIO_PD_EN |
  75         //BIT_SLP_LDODCXO_PD_EN |
  76         BIT_SLP_LDOCON_PD_EN |
  77         BIT_SLP_LDOVDD25_PD_EN |
  78         //BIT_SLP_LDOVDD28_PD_EN |
  79         //BIT_SLP_LODVDD18_PD_EN |
  80         0
  81         );
  82
  83         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
  84         BIT_SLP_LDO_PD_EN |
  85         BIT_SLP_LDOLPREF_PD_EN |
  86         BIT_SLP_LDOCLSG_PD_EN |
  87         BIT_SLP_LDOUSB_PD_EN |
  88         BIT_SLP_LDOCAMMOT_PD_EN |
  89         BIT_SLP_LDOCAMIO_PD_EN |
  90         BIT_SLP_LDOCAMD_PD_EN |
  91         BIT_SLP_LDOCAMA_PD_EN |
  92         BIT_SLP_LDOSIM2_PD_EN |
  93         //BIT_SLP_LDOSIM1_PD_EN |
  94         //BIT_SLP_LDOSIM0_PD_EN |
  95         BIT_SLP_LDOSD_PD_EN |
  96         0);
  97
  98         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
  99         //BIT_SLP_DCDCCORE_LP_EN |
 100         //BIT_SLP_DCDCMEM_LP_EN |
 101         //BIT_SLP_DCDCARM_LP_EN |
 102         //BIT_SLP_DCDCGEN_LP_EN |
 103         //BIT_SLP_DCDCWPA_LP_EN |
 104         //BIT_SLP_LDORF0_LP_EN |
 105         //BIT_SLP_LDOEMMCCORE_LP_EN |
 106         //BIT_SLP_LDOEMMCIO_LP_EN |
 107         //BIT_SLP_LDODCXO_LP_EN |
 108         //BIT_SLP_LDOCON_LP_EN |
 109         //BIT_SLP_LDOVDD25_LP_EN |
 110         //BIT_SLP_LDOVDD28_LP_EN |
 111         //BIT_SLP_LDOVDD18_LP_EN |
 112         0);
 113
 114         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
 115         BIT_SLP_BG_LP_EN|
 116         //BIT_SLP_LDOCLSG_LP_EN |
 117         //BIT_SLP_LDOUSB_LP_EN |
 118         //BIT_SLP_LDOCAMMOT_LP_EN |
 119         //BIT_SLP_LDOCAMIO_LP_EN |
 120         //BIT_SLP_LDOCAMD_LP_EN |
 121         //BIT_SLP_LDOCAMA_LP_EN |
 122         //BIT_SLP_LDOSIM2_LP_EN |
 123         //BIT_SLP_LDOSIM1_LP_EN |
 124         //BIT_SLP_LDOSIM0_LP_EN |
 125         //BIT_SLP_LDOSD_LP_EN |
 126         0);
 127         /****************************************
 128         *   Following is CP LDO Sleep Control  *
 129         ****************************************/
 130         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 131         BIT_LDO_XTL_EN |
 132         //BIT_LDO_DCXO_EXT_XTL1_EN |
 133         //BIT_LDO_DCXO_EXT_XTL0_EN |
 134         //BIT_LDO_DCXO_XTL2_EN |
 135         //BIT_LDO_DCXO_XTL0_EN |
 136         //BIT_LDO_VDD18_EXT_XTL1_EN |
 137         //BIT_LDO_VDD18_EXT_XTL0_EN |
 138         //BIT_LDO_VDD18_XTL2_EN |
 139         //BIT_LDO_VDD18_XTL0_EN |
 140         //BIT_LDO_VDD28_EXT_XTL1_EN |
 141         //BIT_LDO_VDD28_EXT_XTL0_EN |
 142         //BIT_LDO_VDD28_XTL2_EN |
 143         //BIT_LDO_VDD28_XTL0_EN |
 144         0);
 145
 146         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 147         BIT_LDO_RF0_EXT_XTL1_EN |
 148         BIT_LDO_RF0_EXT_XTL0_EN |
 149         BIT_LDO_RF0_XTL2_EN |
 150         BIT_LDO_RF0_XTL0_EN |
 151         //BIT_LDO_VDD25_EXT_XTL1_EN |
 152         //BIT_LDO_VDD25_EXT_XTL0_EN |
 153         BIT_LDO_VDD25_XTL2_EN |
 154         BIT_LDO_VDD25_XTL0_EN |
 155         //BIT_LDO_CON_EXT_XTL1_EN |
 156         //BIT_LDO_CON_EXT_XTL0_EN |
 157         BIT_LDO_CON_XTL2_EN |
 158         BIT_LDO_CON_XTL0_EN |
 159         0);
 160
 161         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 162         //BIT_LDO_SIM2_EXT_XTL1_EN |
 163         //BIT_LDO_SIM2_EXT_XTL0_EN |
 164         //BIT_LDO_SIM2_XTL2_EN |
 165         //BIT_LDO_SIM2_XTL0_EN |
 166         //BIT_LDO_SIM1_EXT_XTL1_EN |
 167         //BIT_LDO_SIM1_EXT_XTL0_EN |
 168         //BIT_LDO_SIM1_XTL2_EN |
 169         //BIT_LDO_SIM1_XTL0_EN |
 170         //BIT_LDO_SIM0_EXT_XTL1_EN |
 171         //BIT_LDO_SIM0_EXT_XTL0_EN |
 172         //BIT_LDO_SIM0_XTL2_EN |
 173         //BIT_LDO_SIM0_XTL0_EN |
 174         0);
 175
 176         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 177         //BIT_XO_EXT_XTL1_EN |
 178         //BIT_XO_EXT_XTL0_EN |
 179         //BIT_XO_XTL2_EN |
 180         //BIT_XO_XTL0_EN |
 181         //BIT_BG_EXT_XTL1_EN |
 182         //BIT_BG_EXT_XTL0_EN |
 183         BIT_BG_XTL2_EN |
 184         BIT_BG_XTL0_EN |
 185         0);
 186
 187         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 188         //BIT_DCDC_WPA_EXT_XTL1_EN |
 189         //BIT_DCDC_WPA_EXT_XTL0_EN |
 190         //BIT_DCDC_WPA_XTL2_EN |
 191         //BIT_DCDC_WPA_XTL0_EN |
 192         //BIT_DCDC_MEM_EXT_XTL1_EN |
 193         //BIT_DCDC_MEM_EXT_XTL0_EN |
 194         //BIT_DCDC_MEM_XTL2_EN |
 195         //BIT_DCDC_MEM_XTL0_EN |
 196         //BIT_DCDC_GEN_EXT_XTL1_EN |
 197         //BIT_DCDC_GEN_EXT_XTL0_EN |
 198         //BIT_DCDC_GEN_XTL2_EN |
 199         //BIT_DCDC_GEN_XTL0_EN |
 200         //BIT_DCDC_CORE_EXT_XTL1_EN |
 201         //BIT_DCDC_CORE_EXT_XTL0_EN |
 202         BIT_DCDC_CORE_XTL2_EN |
 203         BIT_DCDC_CORE_XTL0_EN |
 204         0);
 205         /************************************************
 206         *   Following is AP/CP LDO D DIE Sleep Control   *
 207         *************************************************/
 208         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 209                 BIT_XTL0_AP_SEL |
 210                 BIT_XTL0_CP0_SEL |
 211                 //BIT_XTL0_CP1_SEL |
 212                 BIT_XTL0_CP2_SEL |
 213                 0
 214         );
 215
 216         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 217                 //BIT_XTL1_AP_SEL |
 218                 BIT_XTL1_CP0_SEL |
 219                 //BIT_XTL1_CP1_SEL |
 220                 //BIT_XTL1_CP2_SEL |
 221                 0
 222         );
 223
 224         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 225                 //BIT_XTL2_AP_SEL |
 226                 //BIT_XTL2_CP0_SEL |
 227                 //BIT_XTL2_CP1_SEL |
 228                 BIT_XTL2_CP2_SEL |
 229                 0
 230         );
 231
 232         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 233                 BIT_XTLBUF0_CP2_SEL |
 234                 //BIT_XTLBUF0_CP1_SEL |
 235                 BIT_XTLBUF0_CP0_SEL |
 236                 BIT_XTLBUF0_AP_SEL  |
 237                 0
 238         );
 239
 240         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 241                 //BIT_XTLBUF1_CP2_SEL |
 242                 //BIT_XTLBUF1_CP1_SEL |
 243                 BIT_XTLBUF1_CP0_SEL |
 244                 BIT_XTLBUF1_AP_SEL  |
 245                 0
 246         );
 247
 248         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 249                 //BIT_MPLL_REF_SEL |
 250                 //BIT_MPLL_CP2_SEL |
 251                 //BIT_MPLL_CP1_SEL |
 252                 //BIT_MPLL_CP0_SEL |
 253                 BIT_MPLL_AP_SEL  |
 254                 0
 255         );
 256
 257         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 258                 //BIT_DPLL_REF_SEL |
 259                 BIT_DPLL_CP2_SEL |
 260                 //BIT_DPLL_CP1_SEL |
 261                 BIT_DPLL_CP0_SEL |
 262                 BIT_DPLL_AP_SEL  |
 263                 0
 264         );
 265
 266         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
 267                 //BIT_TDPLL_REF_SEL |
 268                 BIT_TDPLL_CP2_SEL |
 269                 BIT_TDPLL_CP1_SEL |
 270                 BIT_TDPLL_CP0_SEL |
 271                 BIT_TDPLL_AP_SEL  |
 272                 0
 273         );
 274
 275         if(ANA_GET_CHIP_ID() == 0x2711a000)
 276         {
 277                 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
 278                         //BIT_WPLL_REF_SEL |
 279                         //BIT_WPLL_CP2_SEL |
 280                         //BIT_WPLL_CP1_SEL |
 281                         BIT_WPLL_CP0_SEL |
 282                         //BIT_WPLL_AP_SEL  |
 283                         0
 284                 );
 285         } else {
 286                 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 287                         //BIT_XTLBUF1_CP2_SEL |
 288                         //BIT_XTLBUF1_CP1_SEL |
 289                         BIT_XTLBUF1_CP0_SEL |
 290                         //BIT_XTLBUF1_AP_SEL  |
 291                         0
 292                 );
 293
 294                 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
 295                         BIT_WPLL_REF_SEL |
 296                         //BIT_WPLL_CP2_SEL |
 297                         //BIT_WPLL_CP1_SEL |
 298                         BIT_WPLL_CP0_SEL |
 299                         //BIT_WPLL_AP_SEL  |
 300                         0
 301                 );
 302
 303                 CHIP_REG_SET(REG_AON_CLK_FM_CFG,
 304                         //BIT_CLK_FM_PAD_SEL |
 305                         //BIT_CLK_FM_SEL |
 306                         0
 307                 );
 308
 309                 CHIP_REG_SET(REG_AON_APB_GPS_26M_REF_SEL,
 310                         //BIT_XTLBUF1_GPS_SEL |
 311                         BIT_XTLBUF0_GPS_SEL |
 312                         //BIT_GPS_26M_REF_SEL |
 313                         0
 314                 );
 315         }
 316
 317         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 318                 //BIT_CPLL_REF_SEL |
 319                 BIT_CPLL_CP2_SEL |
 320                 //BIT_CPLL_CP1_SEL |
 321                 //BIT_CPLL_CP0_SEL |
 322                 //BIT_CPLL_AP_SEL  |
 323                 0
 324         );
 325
 326         CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
 327                 //BIT_WIFIPLL1_REF_SEL |
 328                 BIT_WIFIPLL1_CP2_SEL |
 329                 //BIT_WIFIPLL1_CP1_SEL |
 330                 //BIT_WIFIPLL1_CP0_SEL |
 331                 //BIT_WIFIPLL1_AP_SEL |
 332                 0
 333         );
 334
 335         CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
 336                 //BIT_WIFIPLL2_REF_SEL |
 337                 BIT_WIFIPLL2_CP2_SEL |
 338                 //BIT_WIFIPLL2_CP1_SEL |
 339                 //BIT_WIFIPLL2_CP0_SEL |
 340                 //BIT_WIFIPLL2_AP_SEL |
 341                 0
 342         );
 343
 344         CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN,
 345                 BIT_CGM_208M_AP_EN |
 346                 BIT_CGM_12M_AP_EN |
 347                 BIT_CGM_24M_AP_EN |
 348                 BIT_CGM_48M_AP_EN |
 349                 BIT_CGM_51M2_AP_EN |
 350                 BIT_CGM_64M_AP_EN |
 351                 BIT_CGM_76M8_AP_EN |
 352                 BIT_CGM_96M_AP_EN |
 353                 BIT_CGM_128M_AP_EN |
 354                 BIT_CGM_153M6_AP_EN |
 355                 BIT_CGM_192M_AP_EN |
 356                 BIT_CGM_256M_AP_EN |
 357                 BIT_CGM_384M_AP_EN |
 358                 BIT_CGM_312M_AP_EN |
 359                 BIT_CGM_MPLL_AP_EN |
 360                 //BIT_CGM_WPLL_AP_EN |
 361                 //BIT_CGM_WIFIPLL1_AP_EN |
 362                 BIT_CGM_TDPLL_AP_EN |
 363                 //BIT_CGM_CPLL_AP_EN |
 364                 BIT_CGM_DPLL_AP_EN |
 365                 BIT_CGM_26M_AP_EN |
 366                 0
 367         );
 368         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 369                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 370                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 371                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 372                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 373                 0
 374         );
 375
 376         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 377                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 378                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 379                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 380                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 381                 0
 382         );
 383
 384         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 385                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 386                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 387                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 388                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 389                 0
 390         );
 391
 392         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 393                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 394                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 395                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 396                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 397                 0
 398         );
 399
 400         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 401                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 402                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 403                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 404                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 405                 0
 406         );
 407
 408         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 409                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 410                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 411                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 412                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 413                 0
 414         );
 415
 416         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 417                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 418                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 419                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 420                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 421                 0
 422         );
 423
 424         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 425                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 426                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 427                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 428                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 429                 0
 430         );
 431
 432         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 433                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 434                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 435                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 436                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 437                 0
 438         );
 439
 440         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 441                 BITS_XTL1_WAIT_CNT(0x39)                |
 442                 BITS_XTL0_WAIT_CNT(0x39)                |
 443                 0
 444         );
 445
 446         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 447                 BITS_XTLBUF1_WAIT_CNT(7)                |
 448                 BITS_XTLBUF0_WAIT_CNT(7)                |
 449                 0
 450         );
 451
 452         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 453                 BITS_WPLL_WAIT_CNT(7)                   |
 454                 BITS_TDPLL_WAIT_CNT(7)                  |
 455                 BITS_DPLL_WAIT_CNT(7)                   |
 456                 BITS_MPLL_WAIT_CNT(7)                   |
 457                 0
 458         );
 459
 460         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 461                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 462                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 463                 BITS_CPLL_WAIT_CNT(7)                   |
 464                 0
 465         );
 466
 467         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 468                 BITS_SLP_IN_WAIT_DCDCARM(9)             |
 469                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 470                 0
 471         );
 472 }