3 #include <asm/arch/ldo.h>
4 #include <asm/arch/sc8810_reg_ahb.h>
5 #include <asm/arch/regs_ahb.h>
6 #include <asm/arch/common.h>
7 #include <asm/arch/adi_hal_internal.h>
8 #include <asm/u-boot.h>
11 #include <asm/arch/mfp.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 extern void sprd_gpio_init(void);
15 extern void ADI_init (void);
16 extern int LDO_Init(void);
18 #define GB_SOFT_RST (0x8B00004c)
19 #define BIT_APCP_RST (0x00000040)
20 #define mdelay(n) udelay((n) * 1000)
22 void modem_poweron(void)
25 *(volatile unsigned long *)GB_SOFT_RST &= ~BIT_APCP_RST;
28 void modem_poweroff(void)
31 *(volatile unsigned long *)GB_SOFT_RST |= BIT_APCP_RST;
34 /*Modem download pin,set to high,Modem can not enter downnload mode*/
38 void Init_7702_modem(void)
41 *(volatile unsigned long *)GB_SOFT_RST |= BIT_APCP_RST;
43 /*Modem AP_CP Rts pin set to low (default)*/
44 gpio_direction_output(AP_CP_RTS, 1);
45 gpio_set_value(AP_CP_RTS, 0);
48 /*Modem download pin,set to high,Modem can not enter downnload mode*/
51 /*Modem CP_Life status*/
52 gpio_direction_output(CP_AP_LIV, 0);
56 void init_calibration_gpio(void)
58 gpio_direction_output(AP_CP_RTS, 1);
59 gpio_set_value(AP_CP_RTS, 0);
61 gpio_direction_output(CP_AP_RDY, 0);
62 //gpio_set_value(CP_AP_RDY, 0);
64 gpio_direction_output(CP_AP_RTS, 0);
65 //gpio_set_value(CP_AP_RTS, 0);
67 gpio_direction_output(AP_CP_RDY, 1);
68 gpio_set_value(AP_CP_RDY, 1);
70 gpio_direction_output(CP_AP_LIV, 0);
71 //gpio_set_value(CP_AP_LIV, 0);
74 void init_calibration_mode(void)
79 init_calibration_gpio();
82 #define PIN_CTL_REG 0x8C000000
83 static void chip_init(void)
85 //ANA_REG_SET(ANA_ADIE_CHIP_ID,0);
86 /* setup pins configration when LDO shutdown*/
87 //__raw_writel(0x1fff00, PIN_CTL_REG);
88 *(volatile unsigned int *)PIN_CTL_REG = 0x1fff00;
90 /*sim ldo constrol swith config*/
91 /*should be changed with different project defination*/
92 ANA_REG_OR(ANA_LDO_SWITCH,0x0f);/*switch sim0,1,2,wpadcdc to cp side*/
94 /*adie headset detection config*/
96 //ANA_REG_OR(0x82000830,0x02);//7710 usb ldo on
97 /*cp jtag func and pin config*/
98 //CHIP_REG_AND(0x8B0000B0, ~0x780000);//pin eb
99 //CHIP_REG_SET(0x8C00043c, 0x00158);
100 //CHIP_REG_SET(0x8C000440, 0x00198);
101 //CHIP_REG_SET(0x8C000444, 0x00118);
102 //CHIP_REG_SET(0x8C000448, 0x00198);
103 //CHIP_REG_SET(0x8C00044c, 0x00198);
106 #ifdef CONFIG_GENERIC_MMC
107 static unsigned long sdio_func_cfg[] = {
108 MFP_CFG_X(SD0_CLK0, AF0, DS3, F_PULL_NONE, S_PULL_NONE, IO_Z),
109 MFP_CFG_X(SD0_CLK1, AF0, DS3, F_PULL_NONE, S_PULL_NONE, IO_Z),
110 MFP_CFG_X(SD0_CMD, AF0, DS0, F_PULL_UP, S_PULL_NONE, IO_Z),
111 MFP_CFG_X(SD0_D0, AF0, DS0, F_PULL_UP, S_PULL_NONE, IO_Z),
112 MFP_CFG_X(SD0_D1, AF0, DS0, F_PULL_DOWN, S_PULL_NONE, IO_Z),
113 MFP_CFG_X(SD0_D2, AF0, DS0, F_PULL_DOWN, S_PULL_NONE, IO_Z),
114 MFP_CFG_X(SD0_D3, AF0, DS0, F_PULL_DOWN, S_PULL_NONE, IO_Z),
117 static unsigned long sdcard_detect_gpio_cfg =
118 MFP_CFG_X(CP_RFCTL11, AF3, DS1, F_PULL_UP,S_PULL_NONE, IO_Z);
120 void sprd_config_sdio_pins(void)
122 sprd_mfp_config(sdio_func_cfg, ARRAY_SIZE(sdio_func_cfg));
123 sprd_mfp_config(&sdcard_detect_gpio_cfg, 1);
125 int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
126 int board_mmc_init(bd_t *bd)
128 ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
131 REG32(AHB_CTL0) |= BIT_4;
132 REG32(AHB_SOFT_RST) |= BIT_12;
133 REG32(AHB_SOFT_RST) &= ~BIT_12;
134 LDO_SetVoltLevel(LDO_LDO_SDIO0, LDO_VOLT_LEVEL1);
135 LDO_TurnOnLDO(LDO_LDO_SDIO0);
136 sprd_config_sdio_pins();
138 for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
139 if (mv_sdh_init(mmc_base_address[i], SDIO_BASE_CLK_96M,
150 gd->bd->bi_arch_number = MACH_TYPE_OPENPHONE;
151 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
163 gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,