1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
6 /***************************************************************************************************************************/
7 /* VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
8 /* AP x x v v v v v v v v v x v v v v v v v */
9 /* CP0 x x v v v x x x x v x x x x x x x x x */
10 /* CP1 x x v x x x x x x x x x x x x x x x x */
11 /* CP2 x x v v x v x x x v x x x x x x x x x */
12 /* EX0 x x x v x x x x x x x x x x x x x x x */
13 /* EX1 x x x x v x x x x x x x x x x x x x x */
14 /* EX2 x x x v x x x x x x x x x x x x x x x */
15 /***************************************************************************************************************************/
17 /***************************************************************************************************************************/
18 /* CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA LPGEN LPARM LPMEM LPCORE LPBG BG */
19 /* AP v v v v v v v v v v v x v v v v v v */
20 /* CP0 x x x x x x x x x x x x x x x x x x */
21 /* CP1 x x x x x x x x x x x x x x x x x x */
22 /* CP2 x x x x x x v v x x x x x x x x x x */
23 /* EX0 x x x x x x x x v x x x x x x x x x */
24 /* EX1 x x x x x x x x x x x x x x x x x x */
25 /* EX2 x x x x x x x x x x x x x x x x x x */
26 /***************************************************************************************************************************/
28 void init_ldo_sleep_gr(void)
30 ANA_REG_OR(ANA_REG_GLB_LDO_DCDC_PD_RTCSET, (BIT_LDO_RF1_PD_RTCSET | BIT_DCDC_WRF_PD_RTCSET | BIT_LDO_RF2_PD_RTCSET));
31 ANA_REG_AND(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, (~(BIT_LDO_RF1_PD_RTCSET | BIT_DCDC_WRF_PD_RTCSET | BIT_LDO_RF2_PD_RTCSET)));
32 ANA_REG_OR(ANA_REG_GLB_LDO_PD_CTRL, (BIT_DCDC_WPA_PD));
34 /**********************************************
35 * Following is AP LDO A DIE Sleep Control *
36 *********************************************/
37 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
39 BIT_SLP_DCDC_OTP_PD_EN |
40 //BIT_SLP_DCDCGEN_PD_EN |
41 //BIT_SLP_DCDCWPA_PD_EN |
42 //BIT_SLP_DCDCWRF_PD_EN |
43 BIT_SLP_DCDCARM_PD_EN |
44 BIT_SLP_LDOEMMCCORE_PD_EN |
45 BIT_SLP_LDOEMMCIO_PD_EN |
46 //BIT_SLP_LDORF2_PD_EN |
47 //BIT_SLP_LDORF1_PD_EN |
48 BIT_SLP_LDORF0_PD_EN |
49 BIT_SLP_LDOVDD25_PD_EN |
50 //BIT_SLP_LDOVDD28_PD_EN |
51 //BIT_SLP_LDOVDD18_PD_EN |
55 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
57 BIT_SLP_LDOLPREF_PD_EN |
58 BIT_SLP_LDOCLSG_PD_EN |
59 BIT_SLP_LDOUSB_PD_EN |
60 BIT_SLP_LDOCAMMOT_PD_EN |
61 BIT_SLP_LDOCAMIO_PD_EN |
62 BIT_SLP_LDOCAMD_PD_EN |
63 BIT_SLP_LDOCAMA_PD_EN |
64 BIT_SLP_LDOSIM2_PD_EN |
65 //BIT_SLP_LDOSIM1_PD_EN |
66 //BIT_SLP_LDOSIM0_PD_EN |
68 BIT_SLP_LDOAVDD18_PD_EN |
72 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
73 //BIT_SLP_DCDC_BG_LP_EN |
74 //BIT_SLP_DCDCCORE_LP_EN |
75 //BIT_SLP_DCDCMEM_LP_EN |
76 //BIT_SLP_DCDCARM_LP_EN |
77 //BIT_SLP_DCDCGEN_LP_EN |
78 //BIT_SLP_DCDCWPA_LP_EN |
79 //BIT_SLP_DCDCWRF_LP_EN |
80 //BIT_SLP_LDOEMMCCORE_LP_EN |
81 //BIT_SLP_LDOEMMCIO_LP_EN |
82 //BIT_SLP_LDORF2_LP_EN |
83 //BIT_SLP_LDORF1_LP_EN |
84 //BIT_SLP_LDORF0_LP_EN |
88 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
90 //BIT_SLP_LDOVDD25_LP_EN |
91 //BIT_SLP_LDOVDD28_LP_EN |
92 //BIT_SLP_LDOVDD18_LP_EN |
93 //BIT_SLP_LDOCLSG_LP_EN |
94 //BIT_SLP_LDOUSB_LP_EN |
95 //BIT_SLP_LDOCAMMOT_LP_EN |
96 //BIT_SLP_LDOCAMIO_LP_EN |
97 //BIT_SLP_LDOCAMD_LP_EN |
98 //BIT_SLP_LDOCAMA_LP_EN |
99 //BIT_SLP_LDOSIM2_LP_EN |
100 //BIT_SLP_LDOSIM1_LP_EN |
101 //BIT_SLP_LDOSIM0_LP_EN |
102 //BIT_SLP_LDOSD_LP_EN |
103 //BIT_SLP_LDOAVDD18_LP_EN |
107 /****************************************
108 * Following is CP LDO Sleep Control *
109 ****************************************/
111 ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
112 //BIT_LDO_VDD18_EXT_XTL2_EN |
113 //BIT_LDO_VDD18_EXT_XTL1_EN |
114 //BIT_LDO_VDD18_EXT_XTL0_EN |
115 //BIT_LDO_VDD18_XTL2_EN |
116 //BIT_LDO_VDD18_XTL1_EN |
117 //BIT_LDO_VDD18_XTL0_EN |
118 //BIT_LDO_VDD28_EXT_XTL2_EN |
119 //BIT_LDO_VDD28_EXT_XTL1_EN |
120 //BIT_LDO_VDD28_EXT_XTL0_EN |
121 //BIT_LDO_VDD28_XTL2_EN |
122 //BIT_LDO_VDD28_XTL1_EN |
123 //BIT_LDO_VDD28_XTL0_EN |
127 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
129 //BIT_LDO_RF1_EXT_XTL2_EN |
130 //BIT_LDO_RF1_EXT_XTL1_EN |
131 //BIT_LDO_RF1_EXT_XTL0_EN |
132 //BIT_LDO_RF1_XTL2_EN |
133 //BIT_LDO_RF1_XTL1_EN |
134 //BIT_LDO_RF1_XTL0_EN |
135 //BIT_LDO_RF0_EXT_XTL2_EN |
136 //BIT_LDO_RF0_EXT_XTL1_EN |
137 //BIT_LDO_RF0_EXT_XTL0_EN |
138 BIT_LDO_RF0_XTL2_EN |
139 BIT_LDO_RF0_XTL1_EN |
140 BIT_LDO_RF0_XTL0_EN |
144 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
145 //BIT_LDO_VDD25_EXT_XTL2_EN |
146 //BIT_LDO_VDD25_EXT_XTL1_EN |
147 //BIT_LDO_VDD25_EXT_XTL0_EN |
148 BIT_LDO_VDD25_XTL2_EN |
149 BIT_LDO_VDD25_XTL1_EN |
150 BIT_LDO_VDD25_XTL0_EN |
151 //BIT_LDO_RF2_EXT_XTL2_EN |
152 //BIT_LDO_RF2_EXT_XTL1_EN |
153 //BIT_LDO_RF2_EXT_XTL0_EN |
154 //BIT_LDO_RF2_XTL2_EN |
155 //BIT_LDO_RF2_XTL1_EN |
156 //BIT_LDO_RF2_XTL0_EN |
160 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
161 //BIT_LDO_AVDD18_EXT_XTL2_EN |
162 //BIT_LDO_AVDD18_EXT_XTL1_EN |
163 //BIT_LDO_AVDD18_EXT_XTL0_EN |
164 //BIT_LDO_AVDD18_XTL2_EN |
165 //BIT_LDO_AVDD18_XTL1_EN |
166 //BIT_LDO_AVDD18_XTL0_EN |
167 //BIT_LDO_SIM2_EXT_XTL2_EN |
168 //BIT_LDO_SIM2_EXT_XTL1_EN |
169 //BIT_LDO_SIM2_EXT_XTL0_EN |
170 //BIT_LDO_SIM2_XTL2_EN |
171 //BIT_LDO_SIM2_XTL1_EN |
172 //BIT_LDO_SIM2_XTL0_EN |
176 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
177 //BIT_DCDC_BG_EXT_XTL2_EN |
178 //BIT_DCDC_BG_EXT_XTL1_EN |
179 //BIT_DCDC_BG_EXT_XTL0_EN |
180 BIT_DCDC_BG_XTL2_EN |
181 BIT_DCDC_BG_XTL1_EN |
182 BIT_DCDC_BG_XTL0_EN |
183 //BIT_BG_EXT_XTL2_EN |
184 //BIT_BG_EXT_XTL1_EN |
185 //BIT_BG_EXT_XTL0_EN |
192 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
193 //BIT_DCDC_WRF_XTL2_EN |
194 //BIT_DCDC_WRF_XTL1_EN |
195 //BIT_DCDC_WRF_XTL0_EN |
196 //BIT_DCDC_WPA_XTL2_EN |
197 //BIT_DCDC_WPA_XTL1_EN |
198 //BIT_DCDC_WPA_XTL0_EN |
199 BIT_DCDC_MEM_XTL2_EN |
200 BIT_DCDC_MEM_XTL1_EN |
201 BIT_DCDC_MEM_XTL0_EN |
202 BIT_DCDC_GEN_XTL2_EN |
203 BIT_DCDC_GEN_XTL1_EN |
204 BIT_DCDC_GEN_XTL0_EN |
205 BIT_DCDC_CORE_XTL2_EN |
206 BIT_DCDC_CORE_XTL1_EN |
207 BIT_DCDC_CORE_XTL0_EN |
211 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
212 //BIT_DCDC_WRF_EXT_XTL2_EN |
213 //BIT_DCDC_WRF_EXT_XTL1_EN |
214 //BIT_DCDC_WRF_EXT_XTL0_EN |
215 //BIT_DCDC_WPA_EXT_XTL2_EN |
216 //BIT_DCDC_WPA_EXT_XTL1_EN |
217 //BIT_DCDC_WPA_EXT_XTL0_EN |
218 //BIT_DCDC_MEM_EXT_XTL2_EN |
219 //BIT_DCDC_MEM_EXT_XTL1_EN |
220 //BIT_DCDC_MEM_EXT_XTL0_EN |
221 //BIT_DCDC_GEN_EXT_XTL2_EN |
222 //BIT_DCDC_GEN_EXT_XTL1_EN |
223 //BIT_DCDC_GEN_EXT_XTL0_EN |
224 //BIT_DCDC_CORE_EXT_XTL2_EN |
225 //BIT_DCDC_CORE_EXT_XTL1_EN |
226 //BIT_DCDC_CORE_EXT_XTL0_EN |
230 /************************************************
231 * Following is AP/CP LDO D DIE Sleep Control *
232 *************************************************/
234 CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
242 CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
250 CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
258 CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
259 BIT_XTLBUF0_CP2_SEL |
260 BIT_XTLBUF0_CP1_SEL |
261 BIT_XTLBUF0_CP0_SEL |
266 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
267 BIT_XTLBUF1_CP2_SEL |
268 BIT_XTLBUF1_CP1_SEL |
269 BIT_XTLBUF1_CP0_SEL |
274 CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
283 CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
292 CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
293 //BIT_TDPLL_REF_SEL |
301 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
310 CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
319 CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
320 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
321 BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
322 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
323 BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
327 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
328 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
329 BITS_PD_CA7_C0_PWR_ON_DLY(8) |
330 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
331 BITS_PD_CA7_C0_ISO_ON_DLY(2) |
335 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
336 BIT_PD_CA7_C1_FORCE_SHUTDOWN |
337 BITS_PD_CA7_C1_PWR_ON_DLY(8) |
338 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
339 BITS_PD_CA7_C1_ISO_ON_DLY(2) |
343 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
344 BIT_PD_CA7_C2_FORCE_SHUTDOWN |
345 BITS_PD_CA7_C2_PWR_ON_DLY(8) |
346 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
347 BITS_PD_CA7_C2_ISO_ON_DLY(2) |
351 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
352 BIT_PD_CA7_C3_FORCE_SHUTDOWN |
353 BITS_PD_CA7_C3_PWR_ON_DLY(8) |
354 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
355 BITS_PD_CA7_C3_ISO_ON_DLY(2) |
359 CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
360 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
361 BITS_PD_AP_SYS_PWR_ON_DLY(8) |
362 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
363 BITS_PD_AP_SYS_ISO_ON_DLY(6) |
367 CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
368 BIT_PD_MM_TOP_FORCE_SHUTDOWN |
369 BITS_PD_MM_TOP_PWR_ON_DLY(8) |
370 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
371 BITS_PD_MM_TOP_ISO_ON_DLY(4) |
375 CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
376 BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
377 BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
378 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
379 BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
383 CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
384 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
385 BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
386 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
387 BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
391 CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
392 BITS_XTL1_WAIT_CNT(0x39) |
393 BITS_XTL0_WAIT_CNT(0x39) |
397 CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
398 BITS_XTLBUF1_WAIT_CNT(7) |
399 BITS_XTLBUF0_WAIT_CNT(7) |
403 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
404 BITS_WPLL_WAIT_CNT(7) |
405 BITS_TDPLL_WAIT_CNT(7) |
406 BITS_DPLL_WAIT_CNT(7) |
407 BITS_MPLL_WAIT_CNT(7) |
411 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
412 BITS_WIFIPLL2_WAIT_CNT(7) |
413 BITS_WIFIPLL1_WAIT_CNT(7) |
414 BITS_CPLL_WAIT_CNT(7) |
418 ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
419 BITS_SLP_IN_WAIT_DCDCARM(9) |
420 BITS_SLP_OUT_WAIT_DCDCARM(8) |